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authorJagan Teki <jagan@amarulasolutions.com>2020-05-09 19:56:22 +0300
committerKever Yang <kever.yang@rock-chips.com>2020-05-22 15:53:20 +0300
commit89f2fa0b5e82fa5fa05e5bce0e24bc1d863270ce (patch)
treed4c1e12e9250b6b83df1a24dce4d012f9d19223f /arch
parent99d59069c0a18147b1a475236b0632d085315c43 (diff)
downloadu-boot-89f2fa0b5e82fa5fa05e5bce0e24bc1d863270ce.tar.xz
pci: Add Rockchip PCIe PHY controller driver
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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