riscv:cache:jh7110: add cache driver

support flush_dcache_range interface STARFIVE_JH7110_L2CC_FLUSH

Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>

3 files changed, 66 insertions, 0 deletions

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 6755696b4f..2667c804d8 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -48,3 +48,18 @@ choice
 		bool "GMAC works on auto mode"
 
 endchoice
+
+config STARFIVE_JH7110_L2CC_FLUSH
+ bool "Support Level 2 Cache Controller Flush operation of Starfive JH7110"
+
+if STARFIVE_JH7110_L2CC_FLUSH
+
+config STARFIVE_JH7110_L2CC_FLUSH_START
+ hex "Level 2 Cache Flush operation start"
+ default 0x40000000
+
+config STARFIVE_JH7110_L2CC_FLUSH_SIZE
+ hex "Level 2 Cache Flush operation size"
+ default 0x400000000
+
+endif # STARFIVE_JH7110_L2CC_FLUSH
diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
index 8349d051cc..a2a3ddd7bb 100644
--- a/arch/riscv/cpu/jh7110/Makefile
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -7,5 +7,6 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += cache.o
 endif
 obj-y += pll.o
diff --git a/arch/riscv/cpu/jh7110/cache.c b/arch/riscv/cpu/jh7110/cache.c
new file mode 100644
index 0000000000..470137256d
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cache.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(STARFIVE_JH7110_L2CC_FLUSH)
+#define L2_CACHE_FLUSH64	0x200
+#define L2_CACHE_BASE_ADDR 	0x2010000
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line;
+	volatile unsigned long *flush64;
+
+	/* make sure the address is in the range */
+	if(start > end ||
+		start < CONFIG_STARFIVE_JH7110_L2CC_FLUSH_START ||
+		end > (CONFIG_STARFIVE_JH7110_L2CC_FLUSH_START +
+				CONFIG_STARFIVE_JH7110_L2CC_FLUSH_SIZE))
+		return;
+
+	/*In order to improve the performance, change base addr to a fixed value*/
+	flush64 = (volatile unsigned long *)(L2_CACHE_BASE_ADDR + L2_CACHE_FLUSH64);
+
+	/* memory barrier */
+	mb();
+	for (line = start; line < end; line += CONFIG_SYS_CACHELINE_SIZE) {
+		(*flush64) = line;
+		/* memory barrier */
+		mb();
+	}
+
+	return;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	flush_dcache_range(start,end);
+}
+#endif //SIFIVE_FU540_L2CC_FLUSH