Merge git://git.denx.de/u-boot-socfpga

- Assorted Gen5 fixes

2 files changed, 13 insertions, 1 deletions

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 31681b799d..22042d0de0 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -79,6 +79,8 @@ static const struct {
 	{ 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
 	/* Arria V */
 	{ 0x2d03, "Arria V, D5", "av_d5" },
+	/* Arria V ST/SX */
+	{ 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
 };
 
 static int socfpga_fpga_id(const bool print_id)
@@ -228,10 +230,13 @@ void do_bridge_reset(int enable, unsigned int mask)
 		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
 		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 		writel(iswgrp_handoff[1], &nic301_regs->remap);
+
+		writel(0x7, &reset_manager_base->brg_mod_reset);
+		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 	} else {
 		writel(0, &sysmgr_regs->fpgaintfgrp_module);
 		writel(0, &sdr_ctrl->fpgaport_rst);
-		writel(0, &reset_manager_base->brg_mod_reset);
+		writel(0x7, &reset_manager_base->brg_mod_reset);
 		writel(1, &nic301_regs->remap);
 	}
 }
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 47e63709ad..408e409375 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -138,6 +138,13 @@ void board_init_f(ulong dummy)
 	if (ret)
 		debug("Reset init failed: %d\n", ret);
 
+#ifdef CONFIG_SPL_NAND_DENALI
+	struct socfpga_reset_manager *reset_manager_base =
+		(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+
+	clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4));
+#endif
+
 	/* enable console uart printing */
 	preloader_console_init();