diff options
author | York Sun <yorksun@freescale.com> | 2013-04-01 22:29:11 +0400 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-04-02 00:33:52 +0400 |
commit | 472d546054dadacca91530bad42ad06f6408124e (patch) | |
tree | 3acfccea2d15c21f12651a852d31452d33ea98e0 /board/esd | |
parent | 5644369450635fa5c2967bee55b1ac41f6e988d0 (diff) | |
download | u-boot-472d546054dadacca91530bad42ad06f6408124e.tar.xz |
Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/esd')
-rw-r--r-- | board/esd/common/lcd.c | 10 | ||||
-rw-r--r-- | board/esd/common/lcd.h | 5 | ||||
-rw-r--r-- | board/esd/cpci750/mpsc.c | 2 | ||||
-rw-r--r-- | board/esd/cpci750/mv_eth.h | 7 | ||||
-rw-r--r-- | board/esd/dasa_sim/cmd_dasa_sim.c | 6 | ||||
-rw-r--r-- | board/esd/pmc440/fpga.c | 16 |
6 files changed, 15 insertions, 31 deletions
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 3dfbf3bc91..1a5f6565e5 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -260,7 +260,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Big epson detected */ - reg_byte_swap = FALSE; + reg_byte_swap = false; palette_index = 0x1e2; palette_value = 0x1e4; lcd_depth = 16; @@ -269,7 +269,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Big epson detected (with register swap bug) */ - reg_byte_swap = TRUE; + reg_byte_swap = true; palette_index = 0x1e3; palette_value = 0x1e5; lcd_depth = 16; @@ -278,7 +278,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Small epson detected (704) */ - reg_byte_swap = FALSE; + reg_byte_swap = false; palette_index = 0x15; palette_value = 0x17; lcd_depth = 8; @@ -287,7 +287,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Small epson detected (705) */ - reg_byte_swap = FALSE; + reg_byte_swap = false; palette_index = 0x15; palette_value = 0x17; lcd_depth = 8; @@ -300,7 +300,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * S1D13505 detected */ - reg_byte_swap = TRUE; + reg_byte_swap = true; palette_index = 0x25; palette_value = 0x27; lcd_depth = 16; diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h index 01f6019bb2..5c48b5ad5a 100644 --- a/board/esd/common/lcd.h +++ b/board/esd/common/lcd.h @@ -35,11 +35,6 @@ #define LOAD_LONG(data) SWAP_LONG(data) #define LOAD_SHORT(data) SWAP_SHORT(data) -#ifndef FALSE -#define FALSE 0 -#define TRUE (!FALSE) -#endif - #define S1D_WRITE_PALETTE(p,i,r,g,b) \ { \ out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \ diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c index c89426d085..4adcec078a 100644 --- a/board/esd/cpci750/mpsc.c +++ b/board/esd/cpci750/mpsc.c @@ -967,7 +967,7 @@ static int galmpsc_set_snoop (int mpsc, int value) * None. * * RETURN: -* True for success, false otherwise. +* true for success, false otherwise. * *******************************************************************************/ diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h index 3d0cb10dd5..94745bcf03 100644 --- a/board/esd/cpci750/mv_eth.h +++ b/board/esd/cpci750/mv_eth.h @@ -47,13 +47,6 @@ ************************************************************************** ************************************************************************** *************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ #ifndef MAX_SKB_FRAGS #define MAX_SKB_FRAGS 0 diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 0014808762..ccea7152c2 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -30,10 +30,6 @@ #define OK 0 #define ERROR (-1) -#define TRUE 1 -#define FALSE 0 - - extern u_long pci9054_iobase; @@ -97,7 +93,7 @@ static int PciEepromWriteLongVPD (int offs, unsigned int value) } } - return TRUE; + return true; } diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index f92bbff291..d38cc96066 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -113,7 +113,7 @@ void fpga_serialslave_init(void) { debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__, __LINE__); - fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ + fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ } @@ -188,7 +188,7 @@ int fpga_done_fn(int cookie) int fpga_pre_config_fn(int cookie) { debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(TRUE); + fpga_reset(true); /* release init# */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT); @@ -213,9 +213,9 @@ int fpga_post_config_fn(int cookie) /* enable PLD0..7 pins */ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N); - fpga_reset(TRUE); + fpga_reset(true); udelay (100); - fpga_reset(FALSE); + fpga_reset(false); udelay (100); FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); @@ -296,7 +296,7 @@ void ngcc_fpga_serialslave_init(void) __FUNCTION__, __LINE__); /* make sure program pin is inactive */ - ngcc_fpga_pgm_fn (FALSE, FALSE, 0); + ngcc_fpga_pgm_fn(false, false, 0); } /* @@ -382,10 +382,10 @@ int ngcc_fpga_pre_config_fn(int cookie) pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - ngcc_fpga_reset(TRUE); + ngcc_fpga_reset(true); FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00); - ngcc_fpga_reset(TRUE); + ngcc_fpga_reset(true); return 0; } @@ -401,7 +401,7 @@ int ngcc_fpga_post_config_fn(int cookie) debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__); udelay (100); - ngcc_fpga_reset(FALSE); + ngcc_fpga_reset(false); FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); |