imx8ulp_evk: Update the DDR timing

Update the dram timing to support PLL bypass mode
for F1.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

1 files changed, 102 insertions, 102 deletions

diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 09240999ce..1878ca593a 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -2,7 +2,7 @@
 /*
  * Copyright 2021 NXP
  *
- * Generated code from MX8M_DDR_tool
+ * Generated code from MX8ULP_DDR_tool
  *
  */
 
@@ -16,10 +16,10 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06002c, 0x17702 },	/* 11 */
 	{ 0x2e060030, 0x5 },	/* 12 */
 	{ 0x2e060034, 0x61 },	/* 13 */
-	{ 0x2e060038, 0xce3f },	/* 14 */
-	{ 0x2e06003c, 0x80e70 },	/* 15 */
+	{ 0x2e060038, 0x4b00 },	/* 14 */
+	{ 0x2e06003c, 0x2edfa },	/* 15 */
 	{ 0x2e060040, 0x5 },	/* 16 */
-	{ 0x2e060044, 0x210 },	/* 17 */
+	{ 0x2e060044, 0xc0 },	/* 17 */
 	{ 0x2e060048, 0x19c7d },	/* 18 */
 	{ 0x2e06004c, 0x101cdf },	/* 19 */
 	{ 0x2e060050, 0x5 },	/* 20 */
@@ -31,56 +31,56 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e060068, 0xa },	/* 26 */
 	{ 0x2e06006c, 0x19 },	/* 27 */
 	{ 0x2e060078, 0x2020200 },	/* 30 */
-	{ 0x2e06007c, 0x160b },	/* 31 */
+	{ 0x2e06007c, 0x1604 },	/* 31 */
 	{ 0x2e060090, 0x10 },	/* 36 */
 	{ 0x2e0600a4, 0x40c040c },	/* 41 */
 	{ 0x2e0600a8, 0x8040614 },	/* 42 */
 	{ 0x2e0600ac, 0x604 },	/* 43 */
 	{ 0x2e0600b0, 0x3090003 },	/* 44 */
 	{ 0x2e0600b4, 0x40002 },	/* 45 */
-	{ 0x2e0600b8, 0xc0011 },	/* 46 */
-	{ 0x2e0600bc, 0xb0509 },	/* 47 */
+	{ 0x2e0600b8, 0x50008 },	/* 46 */
+	{ 0x2e0600bc, 0x40309 },	/* 47 */
 	{ 0x2e0600c0, 0x2106 },	/* 48 */
 	{ 0x2e0600c4, 0xa090017 },	/* 49 */
 	{ 0x2e0600c8, 0x8200016 },	/* 50 */
 	{ 0x2e0600cc, 0xa0a },	/* 51 */
 	{ 0x2e0600d0, 0x4000694 },	/* 52 */
 	{ 0x2e0600d4, 0xa0a0804 },	/* 53 */
-	{ 0x2e0600d8, 0x4002432 },	/* 54 */
+	{ 0x2e0600d8, 0x4000d29 },	/* 54 */
 	{ 0x2e0600dc, 0xa0a0804 },	/* 55 */
 	{ 0x2e0600e0, 0x4004864 },	/* 56 */
 	{ 0x2e0600e4, 0x2030404 },	/* 57 */
-	{ 0x2e0600e8, 0x5040400 },	/* 58 */
-	{ 0x2e0600ec, 0x80b0a06 },	/* 59 */
+	{ 0x2e0600e8, 0x4040400 },	/* 58 */
+	{ 0x2e0600ec, 0x80b0a04 },	/* 59 */
 	{ 0x2e0600f0, 0x7010100 },	/* 60 */
-	{ 0x2e0600f4, 0x4150b },	/* 61 */
+	{ 0x2e0600f4, 0x41507 },	/* 61 */
 	{ 0x2e0600fc, 0x1010000 },	/* 63 */
 	{ 0x2e060100, 0x1000000 },	/* 64 */
 	{ 0x2e060104, 0xe0403 },	/* 65 */
 	{ 0x2e060108, 0xb3 },	/* 66 */
-	{ 0x2e06010c, 0x4a },	/* 67 */
-	{ 0x2e060110, 0x3fd },	/* 68 */
+	{ 0x2e06010c, 0x1b },	/* 67 */
+	{ 0x2e060110, 0x16e },	/* 68 */
 	{ 0x2e060114, 0x94 },	/* 69 */
 	{ 0x2e060118, 0x803 },	/* 70 */
 	{ 0x2e06011c, 0x5 },	/* 71 */
 	{ 0x2e060120, 0x70000 },	/* 72 */
-	{ 0x2e060124, 0x25000f },	/* 73 */
-	{ 0x2e060128, 0x4a0078 },	/* 74 */
+	{ 0x2e060124, 0xe000f },	/* 73 */
+	{ 0x2e060128, 0x4a0026 },	/* 74 */
 	{ 0x2e06012c, 0x4000f9 },	/* 75 */
 	{ 0x2e060130, 0x120103 },	/* 76 */
 	{ 0x2e060134, 0x50005 },	/* 77 */
-	{ 0x2e060138, 0x8070005 },	/* 78 */
+	{ 0x2e060138, 0x7070005 },	/* 78 */
 	{ 0x2e06013c, 0x505010d },	/* 79 */
 	{ 0x2e060140, 0x101030a },	/* 80 */
 	{ 0x2e060144, 0x30a0505 },	/* 81 */
 	{ 0x2e060148, 0x5050101 },	/* 82 */
 	{ 0x2e06014c, 0x1030a },	/* 83 */
 	{ 0x2e060150, 0xe000e },	/* 84 */
-	{ 0x2e060154, 0x4c004c },	/* 85 */
+	{ 0x2e060154, 0x1c001c },	/* 85 */
 	{ 0x2e060158, 0x980098 },	/* 86 */
 	{ 0x2e06015c, 0x3050505 },	/* 87 */
 	{ 0x2e060160, 0x3010403 },	/* 88 */
-	{ 0x2e060164, 0x4050505 },	/* 89 */
+	{ 0x2e060164, 0x3050505 },	/* 89 */
 	{ 0x2e060168, 0x3010403 },	/* 90 */
 	{ 0x2e06016c, 0x8050505 },	/* 91 */
 	{ 0x2e060170, 0x3010403 },	/* 92 */
@@ -101,12 +101,12 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0601b4, 0x2cc0 },	/* 109 */
 	{ 0x2e0601b8, 0x2cc0 },	/* 110 */
 	{ 0x2e0601c0, 0x4e5 },	/* 112 */
-	{ 0x2e0601c4, 0xff40 },	/* 113 */
-	{ 0x2e0601c8, 0xff40 },	/* 114 */
-	{ 0x2e0601cc, 0xff40 },	/* 115 */
-	{ 0x2e0601d0, 0xff40 },	/* 116 */
-	{ 0x2e0601d4, 0xff40 },	/* 117 */
-	{ 0x2e0601dc, 0x1beb },	/* 119 */
+	{ 0x2e0601c4, 0x5b80 },	/* 113 */
+	{ 0x2e0601c8, 0x5b80 },	/* 114 */
+	{ 0x2e0601cc, 0x5b80 },	/* 115 */
+	{ 0x2e0601d0, 0x5b80 },	/* 116 */
+	{ 0x2e0601d4, 0x5b80 },	/* 117 */
+	{ 0x2e0601dc, 0xa02 },	/* 119 */
 	{ 0x2e0601e0, 0x200c0 },	/* 120 */
 	{ 0x2e0601e4, 0x200c0 },	/* 121 */
 	{ 0x2e0601e8, 0x200c0 },	/* 122 */
@@ -138,9 +138,9 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0602a8, 0xd0005 },	/* 170 */
 	{ 0x2e0602ac, 0x404 },	/* 171 */
 	{ 0x2e0602b0, 0xd },	/* 172 */
-	{ 0x2e0602b4, 0x1b0035 },	/* 173 */
-	{ 0x2e0602b8, 0x4040042 },	/* 174 */
-	{ 0x2e0602bc, 0x42 },	/* 175 */
+	{ 0x2e0602b4, 0xa0014 },	/* 173 */
+	{ 0x2e0602b8, 0x4040018 },	/* 174 */
+	{ 0x2e0602bc, 0x18 },	/* 175 */
 	{ 0x2e0602c0, 0x35006a },	/* 176 */
 	{ 0x2e0602c4, 0x4040084 },	/* 177 */
 	{ 0x2e0602c8, 0x84 },	/* 178 */
@@ -168,13 +168,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e060390, 0x30000 },	/* 228 */
 	{ 0x2e060394, 0x1000200 },	/* 229 */
 	{ 0x2e060398, 0x310040 },	/* 230 */
-	{ 0x2e06039c, 0x20002 },	/* 231 */
+	{ 0x2e06039c, 0x20008 },	/* 231 */
 	{ 0x2e0603a0, 0x400100 },	/* 232 */
-	{ 0x2e0603a4, 0x80108 },	/* 233 */
+	{ 0x2e0603a4, 0x80060 },	/* 233 */
 	{ 0x2e0603a8, 0x1000200 },	/* 234 */
 	{ 0x2e0603ac, 0x2100040 },	/* 235 */
 	{ 0x2e0603b0, 0x10 },	/* 236 */
-	{ 0x2e0603b4, 0xe0003 },	/* 237 */
+	{ 0x2e0603b4, 0x50003 },	/* 237 */
 	{ 0x2e0603b8, 0x100001b },	/* 238 */
 	{ 0x2e0603d8, 0xffff0b00 },	/* 246 */
 	{ 0x2e0603dc, 0x1010001 },	/* 247 */
@@ -399,7 +399,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608ec, 0x1320001 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
-	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
+	{ 0x2e0608fc, 0x1b1b0000 },	/* 575 */
 	{ 0x2e060900, 0x21 },	/* 576 */
 	{ 0x2e060904, 0xa },	/* 577 */
 	{ 0x2e060908, 0x166 },	/* 578 */
@@ -410,13 +410,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06091c, 0x432 },	/* 583 */
 	{ 0x2e060920, 0xdfc },	/* 584 */
 	{ 0x2e060924, 0x204 },	/* 585 */
-	{ 0x2e060928, 0x7fa },	/* 586 */
+	{ 0x2e060928, 0x2dc },	/* 586 */
 	{ 0x2e06092c, 0x200 },	/* 587 */
 	{ 0x2e060930, 0x200 },	/* 588 */
 	{ 0x2e060934, 0x200 },	/* 589 */
 	{ 0x2e060938, 0x200 },	/* 590 */
-	{ 0x2e06093c, 0x17ee },	/* 591 */
-	{ 0x2e060940, 0x4fc4 },	/* 592 */
+	{ 0x2e06093c, 0x894 },	/* 591 */
+	{ 0x2e060940, 0x1c98 },	/* 592 */
 	{ 0x2e060944, 0x204 },	/* 593 */
 	{ 0x2e060948, 0x1006 },	/* 594 */
 	{ 0x2e06094c, 0x200 },	/* 595 */
@@ -438,7 +438,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06098c, 0x2010000 },	/* 611 */
 	{ 0x2e060990, 0x6000200 },	/* 612 */
 	{ 0x2e060994, 0x3000a06 },	/* 613 */
-	{ 0x2e060998, 0x2000c06 },	/* 614 */
+	{ 0x2e060998, 0x2000c03 },	/* 614 */
 };
 
 /** PI settings **/
@@ -518,22 +518,22 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e062260, 0x10001 },	/* 152 */
 	{ 0x2e062274, 0x401 },	/* 157 */
 	{ 0x2e06227c, 0x10000 },	/* 159 */
-	{ 0x2e062284, 0x6010000 },	/* 161 */
+	{ 0x2e062284, 0x2010000 },	/* 161 */
 	{ 0x2e062288, 0xb },	/* 162 */
 	{ 0x2e06228c, 0x34 },	/* 163 */
-	{ 0x2e062290, 0x36 },	/* 164 */
+	{ 0x2e062290, 0x34 },	/* 164 */
 	{ 0x2e062294, 0x2003c },	/* 165 */
 	{ 0x2e062298, 0x2000200 },	/* 166 */
 	{ 0x2e06229c, 0xc040c04 },	/* 167 */
 	{ 0x2e0622a0, 0xe1406 },	/* 168 */
 	{ 0x2e0622a4, 0xb3 },	/* 169 */
-	{ 0x2e0622a8, 0x4a },	/* 170 */
-	{ 0x2e0622ac, 0x3fd },	/* 171 */
+	{ 0x2e0622a8, 0x1b },	/* 170 */
+	{ 0x2e0622ac, 0x16e },	/* 171 */
 	{ 0x2e0622b0, 0x94 },	/* 172 */
 	{ 0x2e0622b4, 0x4000803 },	/* 173 */
 	{ 0x2e0622b8, 0x1010404 },	/* 174 */
 	{ 0x2e0622bc, 0x1501 },	/* 175 */
-	{ 0x2e0622c0, 0x1a0018 },	/* 176 */
+	{ 0x2e0622c0, 0x1a0016 },	/* 176 */
 	{ 0x2e0622c4, 0x1000100 },	/* 177 */
 	{ 0x2e0622c8, 0x100 },	/* 178 */
 	{ 0x2e0622d0, 0x5040303 },	/* 180 */
@@ -542,15 +542,15 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e0622e8, 0x2060404 },	/* 186 */
 	{ 0x2e0622ec, 0x2020402 },	/* 187 */
 	{ 0x2e0622f0, 0x3102 },	/* 188 */
-	{ 0x2e0622f4, 0x340009 },	/* 189 */
-	{ 0x2e0622f8, 0x36000c },	/* 190 */
+	{ 0x2e0622f4, 0x320009 },	/* 189 */
+	{ 0x2e0622f8, 0x36000a },	/* 190 */
 	{ 0x2e0622fc, 0x101000e },	/* 191 */
 	{ 0x2e062300, 0xd0101 },	/* 192 */
-	{ 0x2e062304, 0x1004201 },	/* 193 */
+	{ 0x2e062304, 0x1001801 },	/* 193 */
 	{ 0x2e062308, 0x1000084 },	/* 194 */
 	{ 0x2e06230c, 0xe000e },	/* 195 */
-	{ 0x2e062310, 0x430100 },	/* 196 */
-	{ 0x2e062314, 0x1000043 },	/* 197 */
+	{ 0x2e062310, 0x190100 },	/* 196 */
+	{ 0x2e062314, 0x1000019 },	/* 197 */
 	{ 0x2e062318, 0x850085 },	/* 198 */
 	{ 0x2e06231c, 0x220f220f },	/* 199 */
 	{ 0x2e062320, 0x101220f },	/* 200 */
@@ -561,8 +561,8 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e062334, 0xc01000 },	/* 205 */
 	{ 0x2e062338, 0xc01000 },	/* 206 */
 	{ 0x2e06233c, 0x21000 },	/* 207 */
-	{ 0x2e062340, 0x11000d },	/* 208 */
-	{ 0x2e062344, 0x140042 },	/* 209 */
+	{ 0x2e062340, 0x2000d },	/* 208 */
+	{ 0x2e062344, 0x140018 },	/* 209 */
 	{ 0x2e062348, 0x190084 },	/* 210 */
 	{ 0x2e06234c, 0x220f0056 },	/* 211 */
 	{ 0x2e062350, 0x101 },	/* 212 */
@@ -575,40 +575,40 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e06236c, 0x5eb },	/* 219 */
 	{ 0x2e062370, 0x20010003 },	/* 220 */
 	{ 0x2e062374, 0x80a0a03 },	/* 221 */
-	{ 0x2e062378, 0x6090506 },	/* 222 */
-	{ 0x2e06237c, 0x2093 },	/* 223 */
-	{ 0x2e062380, 0x2001000c },	/* 224 */
-	{ 0x2e062384, 0x80a0a04 },	/* 225 */
+	{ 0x2e062378, 0x4090403 },	/* 222 */
+	{ 0x2e06237c, 0xbd8 },	/* 223 */
+	{ 0x2e062380, 0x20010005 },	/* 224 */
+	{ 0x2e062384, 0x80a0a03 },	/* 225 */
 	{ 0x2e062388, 0xb090a0c },	/* 226 */
 	{ 0x2e06238c, 0x4126 },	/* 227 */
 	{ 0x2e062390, 0x20020017 },	/* 228 */
 	{ 0x2e062394, 0xa0a08 },	/* 229 */
 	{ 0x2e062398, 0x166 },	/* 230 */
 	{ 0x2e06239c, 0xdfc },	/* 231 */
-	{ 0x2e0623a0, 0x7fa },	/* 232 */
-	{ 0x2e0623a4, 0x4fc4 },	/* 233 */
+	{ 0x2e0623a0, 0x2dc },	/* 232 */
+	{ 0x2e0623a4, 0x1c98 },	/* 233 */
 	{ 0x2e0623a8, 0x1006 },	/* 234 */
 	{ 0x2e0623ac, 0xa03c },	/* 235 */
-	{ 0x2e0623b0, 0x4c000e },	/* 236 */
+	{ 0x2e0623b0, 0x1c000e },	/* 236 */
 	{ 0x2e0623b4, 0x3030098 },	/* 237 */
 	{ 0x2e0623b8, 0x258103 },	/* 238 */
 	{ 0x2e0623bc, 0x17702 },	/* 239 */
 	{ 0x2e0623c0, 0x5 },	/* 240 */
 	{ 0x2e0623c4, 0x61 },	/* 241 */
 	{ 0x2e0623c8, 0xe },	/* 242 */
-	{ 0x2e0623cc, 0xce3f },	/* 243 */
-	{ 0x2e0623d0, 0x80e70 },	/* 244 */
+	{ 0x2e0623cc, 0x4b00 },	/* 243 */
+	{ 0x2e0623d0, 0x17702 },	/* 244 */
 	{ 0x2e0623d4, 0x5 },	/* 245 */
-	{ 0x2e0623d8, 0x210 },	/* 246 */
-	{ 0x2e0623dc, 0x4c },	/* 247 */
+	{ 0x2e0623d8, 0xc0 },	/* 246 */
+	{ 0x2e0623dc, 0x1c },	/* 247 */
 	{ 0x2e0623e0, 0x19c7d },	/* 248 */
-	{ 0x2e0623e4, 0x101cdf },	/* 249 */
+	{ 0x2e0623e4, 0x17702 },	/* 249 */
 	{ 0x2e0623e8, 0x5 },	/* 250 */
 	{ 0x2e0623ec, 0x420 },	/* 251 */
 	{ 0x2e0623f0, 0x1000098 },	/* 252 */
 	{ 0x2e0623f4, 0x310040 },	/* 253 */
-	{ 0x2e0623f8, 0x10002 },	/* 254 */
-	{ 0x2e0623fc, 0x1080040 },	/* 255 */
+	{ 0x2e0623f8, 0x10008 },	/* 254 */
+	{ 0x2e0623fc, 0x600040 },	/* 255 */
 	{ 0x2e062400, 0x10008 },	/* 256 */
 	{ 0x2e062404, 0x2100040 },	/* 257 */
 	{ 0x2e062408, 0x310 },	/* 258 */
@@ -706,18 +706,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064168, 0x1000000 },	/* 90 */
 	{ 0x2e06416c, 0x10001000 },	/* 91 */
 	{ 0x2e064170, 0xc043242 },	/* 92 */
-	{ 0x2e064174, 0xf0c1201 },	/* 93 */
+	{ 0x2e064174, 0xf0c0e01 },	/* 93 */
 	{ 0x2e064178, 0x1000140 },	/* 94 */
 	{ 0x2e06417c, 0xc000120 },	/* 95 */
-	{ 0x2e064180, 0x143 },	/* 96 */
+	{ 0x2e064180, 0x118 },	/* 96 */
 	{ 0x2e064184, 0x1000203 },	/* 97 */
 	{ 0x2e064188, 0x56417032 },	/* 98 */
 	{ 0x2e06418c, 0x8 },	/* 99 */
-	{ 0x2e064190, 0x2c302c3 },	/* 100 */
-	{ 0x2e064194, 0x2c302c3 },	/* 101 */
-	{ 0x2e064198, 0x2c302c3 },	/* 102 */
-	{ 0x2e06419c, 0x2c302c3 },	/* 103 */
-	{ 0x2e0641a0, 0x2c3 },	/* 104 */
+	{ 0x2e064190, 0x2980298 },	/* 100 */
+	{ 0x2e064194, 0x2980298 },	/* 101 */
+	{ 0x2e064198, 0x2980298 },	/* 102 */
+	{ 0x2e06419c, 0x2980298 },	/* 103 */
+	{ 0x2e0641a0, 0x298 },	/* 104 */
 	{ 0x2e0641a4, 0x8000 },	/* 105 */
 	{ 0x2e0641a8, 0x800080 },	/* 106 */
 	{ 0x2e0641ac, 0x800080 },	/* 107 */
@@ -727,7 +727,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0641bc, 0x800080 },	/* 111 */
 	{ 0x2e0641c0, 0x800080 },	/* 112 */
 	{ 0x2e0641c4, 0x800080 },	/* 113 */
-	{ 0x2e0641c8, 0x6b0080 },	/* 114 */
+	{ 0x2e0641c8, 0x1940080 },	/* 114 */
 	{ 0x2e0641cc, 0x1a00001 },	/* 115 */
 	{ 0x2e0641d4, 0x10000 },	/* 117 */
 	{ 0x2e0641d8, 0x80200 },	/* 118 */
@@ -782,18 +782,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064568, 0x1000000 },	/* 346 */
 	{ 0x2e06456c, 0x10001000 },	/* 347 */
 	{ 0x2e064570, 0xc043242 },	/* 348 */
-	{ 0x2e064574, 0xf0c1201 },	/* 349 */
+	{ 0x2e064574, 0xf0c0e01 },	/* 349 */
 	{ 0x2e064578, 0x1000140 },	/* 350 */
 	{ 0x2e06457c, 0xc000120 },	/* 351 */
-	{ 0x2e064580, 0x143 },	/* 352 */
+	{ 0x2e064580, 0x118 },	/* 352 */
 	{ 0x2e064584, 0x1000203 },	/* 353 */
 	{ 0x2e064588, 0x30217465 },	/* 354 */
 	{ 0x2e06458c, 0x8 },	/* 355 */
-	{ 0x2e064590, 0x2c302c3 },	/* 356 */
-	{ 0x2e064594, 0x2c302c3 },	/* 357 */
-	{ 0x2e064598, 0x2c302c3 },	/* 358 */
-	{ 0x2e06459c, 0x2c302c3 },	/* 359 */
-	{ 0x2e0645a0, 0x2c3 },	/* 360 */
+	{ 0x2e064590, 0x2980298 },	/* 356 */
+	{ 0x2e064594, 0x2980298 },	/* 357 */
+	{ 0x2e064598, 0x2980298 },	/* 358 */
+	{ 0x2e06459c, 0x2980298 },	/* 359 */
+	{ 0x2e0645a0, 0x298 },	/* 360 */
 	{ 0x2e0645a4, 0x8000 },	/* 361 */
 	{ 0x2e0645a8, 0x800080 },	/* 362 */
 	{ 0x2e0645ac, 0x800080 },	/* 363 */
@@ -803,7 +803,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0645bc, 0x800080 },	/* 367 */
 	{ 0x2e0645c0, 0x800080 },	/* 368 */
 	{ 0x2e0645c4, 0x800080 },	/* 369 */
-	{ 0x2e0645c8, 0x6b0080 },	/* 370 */
+	{ 0x2e0645c8, 0x1940080 },	/* 370 */
 	{ 0x2e0645cc, 0x1a00001 },	/* 371 */
 	{ 0x2e0645d4, 0x10000 },	/* 373 */
 	{ 0x2e0645d8, 0x80200 },	/* 374 */
@@ -859,18 +859,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064968, 0x1000000 },	/* 602 */
 	{ 0x2e06496c, 0x10001000 },	/* 603 */
 	{ 0x2e064970, 0xc043242 },	/* 604 */
-	{ 0x2e064974, 0xf0c1201 },	/* 605 */
+	{ 0x2e064974, 0xf0c0e01 },	/* 605 */
 	{ 0x2e064978, 0x1000140 },	/* 606 */
 	{ 0x2e06497c, 0xc000120 },	/* 607 */
-	{ 0x2e064980, 0x143 },	/* 608 */
+	{ 0x2e064980, 0x118 },	/* 608 */
 	{ 0x2e064984, 0x1000203 },	/* 609 */
 	{ 0x2e064988, 0x75436012 },	/* 610 */
 	{ 0x2e06498c, 0x8 },	/* 611 */
-	{ 0x2e064990, 0x2c302c3 },	/* 612 */
-	{ 0x2e064994, 0x2c302c3 },	/* 613 */
-	{ 0x2e064998, 0x2c302c3 },	/* 614 */
-	{ 0x2e06499c, 0x2c302c3 },	/* 615 */
-	{ 0x2e0649a0, 0x2c3 },	/* 616 */
+	{ 0x2e064990, 0x2980298 },	/* 612 */
+	{ 0x2e064994, 0x2980298 },	/* 613 */
+	{ 0x2e064998, 0x2980298 },	/* 614 */
+	{ 0x2e06499c, 0x2980298 },	/* 615 */
+	{ 0x2e0649a0, 0x298 },	/* 616 */
 	{ 0x2e0649a4, 0x8000 },	/* 617 */
 	{ 0x2e0649a8, 0x800080 },	/* 618 */
 	{ 0x2e0649ac, 0x800080 },	/* 619 */
@@ -880,7 +880,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0649bc, 0x800080 },	/* 623 */
 	{ 0x2e0649c0, 0x800080 },	/* 624 */
 	{ 0x2e0649c4, 0x800080 },	/* 625 */
-	{ 0x2e0649c8, 0x6b0080 },	/* 626 */
+	{ 0x2e0649c8, 0x1940080 },	/* 626 */
 	{ 0x2e0649cc, 0x1a00001 },	/* 627 */
 	{ 0x2e0649d4, 0x10000 },	/* 629 */
 	{ 0x2e0649d8, 0x80200 },	/* 630 */
@@ -935,18 +935,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064d68, 0x1000000 },	/* 858 */
 	{ 0x2e064d6c, 0x10001000 },	/* 859 */
 	{ 0x2e064d70, 0xc043242 },	/* 860 */
-	{ 0x2e064d74, 0xf0c1201 },	/* 861 */
+	{ 0x2e064d74, 0xf0c0e01 },	/* 861 */
 	{ 0x2e064d78, 0x1000140 },	/* 862 */
 	{ 0x2e064d7c, 0xc000120 },	/* 863 */
-	{ 0x2e064d80, 0x143 },	/* 864 */
+	{ 0x2e064d80, 0x118 },	/* 864 */
 	{ 0x2e064d84, 0x1000203 },	/* 865 */
 	{ 0x2e064d88, 0x32017465 },	/* 866 */
 	{ 0x2e064d8c, 0x8 },	/* 867 */
-	{ 0x2e064d90, 0x2c302c3 },	/* 868 */
-	{ 0x2e064d94, 0x2c302c3 },	/* 869 */
-	{ 0x2e064d98, 0x2c302c3 },	/* 870 */
-	{ 0x2e064d9c, 0x2c302c3 },	/* 871 */
-	{ 0x2e064da0, 0x2c3 },	/* 872 */
+	{ 0x2e064d90, 0x2980298 },	/* 868 */
+	{ 0x2e064d94, 0x2980298 },	/* 869 */
+	{ 0x2e064d98, 0x2980298 },	/* 870 */
+	{ 0x2e064d9c, 0x2980298 },	/* 871 */
+	{ 0x2e064da0, 0x298 },	/* 872 */
 	{ 0x2e064da4, 0x8000 },	/* 873 */
 	{ 0x2e064da8, 0x800080 },	/* 874 */
 	{ 0x2e064dac, 0x800080 },	/* 875 */
@@ -956,7 +956,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064dbc, 0x800080 },	/* 879 */
 	{ 0x2e064dc0, 0x800080 },	/* 880 */
 	{ 0x2e064dc4, 0x800080 },	/* 881 */
-	{ 0x2e064dc8, 0x6b0080 },	/* 882 */
+	{ 0x2e064dc8, 0x1940080 },	/* 882 */
 	{ 0x2e064dcc, 0x1a00001 },	/* 883 */
 	{ 0x2e064dd4, 0x10000 },	/* 885 */
 	{ 0x2e064dd8, 0x80200 },	/* 886 */
@@ -1034,7 +1034,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065868, 0xf0f0f },	/* 1562 */
 	{ 0x2e06586c, 0x241342 },	/* 1563 */
 	{ 0x2e065874, 0x1020000 },	/* 1565 */
-	{ 0x2e065878, 0x701 },	/* 1566 */
+	{ 0x2e065878, 0x10701 },	/* 1566 */
 	{ 0x2e06587c, 0x54 },	/* 1567 */
 	{ 0x2e065880, 0x4102000 },	/* 1568 */
 	{ 0x2e065884, 0x24410 },	/* 1569 */
@@ -1047,7 +1047,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0658a0, 0x4410 },	/* 1576 */
 	{ 0x2e0658a4, 0x4410 },	/* 1577 */
 	{ 0x2e0658b0, 0x60000 },	/* 1580 */
-	{ 0x2e0658b8, 0x66 },	/* 1582 */
+	{ 0x2e0658b8, 0x64 },	/* 1582 */
 	{ 0x2e0658bc, 0x10000 },	/* 1583 */
 	{ 0x2e0658c0, 0x8 },	/* 1584 */
 	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
@@ -1064,8 +1064,8 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065934, 0x40700 },	/* 1613 */
 	{ 0x2e06594c, 0x2 },	/* 1619 */
 	{ 0x2e065958, 0xf3c3 },	/* 1622 */
-	{ 0x2e065964, 0x11542 },	/* 1625 */
-	{ 0x2e065968, 0x30209bf },	/* 1626 */
+	{ 0x2e065964, 0x11742 },	/* 1625 */
+	{ 0x2e065968, 0x3020600 },	/* 1626 */
 	{ 0x2e06596c, 0x30000 },	/* 1627 */
 	{ 0x2e065970, 0x3000300 },	/* 1628 */
 	{ 0x2e065974, 0x3000300 },	/* 1629 */
@@ -1098,7 +1098,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064170, 0xc043e42 },	/* 92 */
 	{ 0x2e064174, 0xf0c1701 },	/* 93 */
 	{ 0x2e064180, 0x187 },	/* 96 */
-	{ 0x2e064184, 0x3010203 },	/* 97 */
+	{ 0x2e064184, 0x3200203 },	/* 97 */
 	{ 0x2e064190, 0x3070307 },	/* 100 */
 	{ 0x2e064194, 0x3070307 },	/* 101 */
 	{ 0x2e064198, 0x3070307 },	/* 102 */
@@ -1109,7 +1109,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064570, 0xc043e42 },	/* 348 */
 	{ 0x2e064574, 0xf0c1701 },	/* 349 */
 	{ 0x2e064580, 0x187 },	/* 352 */
-	{ 0x2e064584, 0x3010203 },	/* 353 */
+	{ 0x2e064584, 0x3200203 },	/* 353 */
 	{ 0x2e064590, 0x3070307 },	/* 356 */
 	{ 0x2e064594, 0x3070307 },	/* 357 */
 	{ 0x2e064598, 0x3070307 },	/* 358 */
@@ -1120,7 +1120,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064970, 0xc043e42 },	/* 604 */
 	{ 0x2e064974, 0xf0c1701 },	/* 605 */
 	{ 0x2e064980, 0x187 },	/* 608 */
-	{ 0x2e064984, 0x3010203 },	/* 609 */
+	{ 0x2e064984, 0x3200203 },	/* 609 */
 	{ 0x2e064990, 0x3070307 },	/* 612 */
 	{ 0x2e064994, 0x3070307 },	/* 613 */
 	{ 0x2e064998, 0x3070307 },	/* 614 */
@@ -1131,7 +1131,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064d70, 0xc043e42 },	/* 860 */
 	{ 0x2e064d74, 0xf0c1701 },	/* 861 */
 	{ 0x2e064d80, 0x187 },	/* 864 */
-	{ 0x2e064d84, 0x3010203 },	/* 865 */
+	{ 0x2e064d84, 0x3200203 },	/* 865 */
 	{ 0x2e064d90, 0x3070307 },	/* 868 */
 	{ 0x2e064d94, 0x3070307 },	/* 869 */
 	{ 0x2e064d98, 0x3070307 },	/* 870 */
@@ -1154,5 +1154,5 @@ struct dram_timing_info2 dram_timing = {
 	.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
 	.phy_f2_cfg = ddr_phy_f2_cfg,
 	.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
-	.fsp_table = { 96, 528, 1056 },
+	.fsp_table = { 96, 192, 1056 },
 };