diff options
author | Yangbo Lu <yangbo.lu@nxp.com> | 2017-11-27 10:40:17 +0300 |
---|---|---|
committer | York Sun <york.sun@nxp.com> | 2017-12-14 00:40:29 +0300 |
commit | 44cdb5b6a10a7eb2e240866cb842e44ff9999960 (patch) | |
tree | 3b83c5a70e36eea5d8df7be254ce02553b7a3668 /board/freescale/ls1088a/ls1088a.c | |
parent | cf71338ee7a1dc16f13a4f1b89f32c624210df45 (diff) | |
download | u-boot-44cdb5b6a10a7eb2e240866cb842e44ff9999960.tar.xz |
armv8: ls1088ardb: support force SDHC mode by hwconfig
The BRDCFG5[SPISDHC] register field of Qixis device is used
to control SPI and SDHC signal routing.
10 = Force SDHC Mode
- SPI_CS[0] is routed to CPLD for SDHC_VS use.
- SPI_CS[1] is unused.
- SPI_CS[2:3] are routed to the TDMRiser slot.
11 = Force eMMC Mode
- SPI_CS[0:3] are routed to the eMMC card.
0X = Auto Mode
- If SDHC_CS_B=0 (SDHC card installed): Use SDHC mode
described above.
- Else SDHC_CS_B=1 (no SDHC card installed): Use eMMC
mode described above.
In default the hardware uses auto mode, but sometimes we need
to use force SDHC mode to support SD card hotplug, or SD sleep
waking up in kernel. This patch is to support force SDHC mode
by hwconfig.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1088a/ls1088a.c')
-rw-r--r-- | board/freescale/ls1088a/ls1088a.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 9daa007590..cb589575b3 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -18,6 +18,7 @@ #include <environment.h> #include <asm/arch-fsl-layerscape/soc.h> #include <asm/arch/ppa.h> +#include <hwconfig.h> #include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -296,6 +297,23 @@ void board_retimer_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); } +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_TARGET_LS1088ARDB + u8 brdcfg5; + + if (hwconfig("esdhc-force-sd")) { + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; + brdcfg5 |= BRDCFG5_FORCE_SD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif + return 0; +} +#endif + int board_init(void) { init_final_memctl_regs(); |