diff options
| author | Pankaj Bansal <pankaj.bansal@nxp.com> | 2018-10-10 11:38:34 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2018-10-10 20:45:28 +0300 |
| commit | 1a048cd65645338069d591108031fa4ebe96d53f (patch) | |
| tree | 0d4cdfa9d279c0326ac544dacfe56028be2fe095 /board/freescale/ls2080ardb | |
| parent | 1ed19a1421691e0238b79f8ac14dc4a65ddd7ad0 (diff) | |
| download | u-boot-1a048cd65645338069d591108031fa4ebe96d53f.tar.xz | |
driver: net: fsl-mc: Add support of multiple phys for dpmac
Till now we have had cases where we had one phy device per dpmac.
Now, with the upcoming products (LX2160AQDS), we have cases, where there
are sometimes two phy devices for one dpmac. One phy for TX lanes and
one phy for RX lanes. to handle such cases, add the support for multiple
phys in ethernet driver. The ethernet link is up if all the phy devices
connected to one dpmac report link up. also the link capabilities are
limited by the weakest phy device.
i.e. say if there are two phys for one dpmac. one operates at 10G without
autoneg and other operate at 1G with autoneg. Then the ethernet interface
will operate at 1G without autoneg.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'board/freescale/ls2080ardb')
| -rw-r--r-- | board/freescale/ls2080ardb/eth_ls2080rdb.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 45f1d60322..62c7a7a315 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -50,21 +50,21 @@ int board_eth_init(bd_t *bis) switch (srds_s1) { case 0x2A: - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); - wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4); break; case 0x4B: - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4); break; default: |