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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-08-17 11:11:03 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-09-02 16:34:12 +0300 |
| commit | f2ff834365296151b24bf8617f1f6dd070bdce9e (patch) | |
| tree | bfe6c4b1a6a55061a28e64df5e4933124eb5673e /board/freescale/mx6sxsabresd | |
| parent | 003fa83c437f62f7558a7f7408b7cd7c31c01276 (diff) | |
| download | u-boot-f2ff834365296151b24bf8617f1f6dd070bdce9e.tar.xz | |
imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/freescale/mx6sxsabresd')
| -rw-r--r-- | board/freescale/mx6sxsabresd/mx6sxsabresd.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index ffc0046fb9..b9af7e7b95 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -566,6 +566,7 @@ static void spl_dram_init(void) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |