diff options
| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2015-06-05 12:59:02 +0300 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-29 00:40:57 +0300 |
| commit | 4b6067ae9ddd2113df18735e4f10d8d40fcb1c1e (patch) | |
| tree | 665cb5e0194930ffe336fec849644c5f9d64ebfb /board/freescale/t104xrdb/cpld.h | |
| parent | 26473945ad6667183296e7edee2a65edf31bb6f7 (diff) | |
| download | u-boot-4b6067ae9ddd2113df18735e4f10d8d40fcb1c1e.tar.xz | |
powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t104xrdb/cpld.h')
| -rw-r--r-- | board/freescale/t104xrdb/cpld.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 0da9a0159b..2fb4105275 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -21,7 +21,11 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ +#if defined(CONFIG_T104XD4RDB) + u8 int_mask; /* 0x15 - Interrupt mask Register */ +#else u8 led_ctl_status; /* 0x15 - LED control and status register */ +#endif u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ u8 boot_override; /* 0x18 - Boot override register */ @@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value)\ cpld_write(offsetof(struct cpld_data, reg), value) +#define MISC_CTL_SG_SEL 0x80 +#define MISC_CTL_AURORA_SEL 0x02 |