ppc: Remove MPC8315ERDB board

This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the last
ARCH_MPC8315 platform, remove that support as well.

Signed-off-by: Tom Rini <trini@konsulko.com>

6 files changed, 0 insertions, 494 deletions

diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
deleted file mode 100644
index f76b0d1d6d..0000000000
--- a/board/freescale/mpc8315erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8315ERDB
-
-config SYS_BOARD
-	default "mpc8315erdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8315ERDB"
-
-endif
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
deleted file mode 100644
index cdac1ac2ee..0000000000
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8315ERDB BOARD
-#M:	Dave Liu <daveliu@freescale.com>
-S:	Orphan (since 2018-05)
-F:	board/freescale/mpc8315erdb/
-F:	include/configs/MPC8315ERDB.h
-F:	configs/MPC8315ERDB_defconfig
-F:	configs/MPC8315ERDB_NANDSPL_defconfig
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
deleted file mode 100644
index 579181999d..0000000000
--- a/board/freescale/mpc8315erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
deleted file mode 100644
index 8ad6d810c7..0000000000
--- a/board/freescale/mpc8315erdb/README
+++ /dev/null
@@ -1,105 +0,0 @@
-Freescale MPC8315ERDB Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
-	To boot the image at 0xFE000000 in NOR flash, use these DIP
-	switch settings for S3 S4:
-
-	+------+	+------+
-	|      |	| **** |
-	| **** |	|      |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	To boot the image at the beginning of NAND flash, use these
-	DIP switch settings for S3 S4:
-
-	+------+	+------+
-	| *    |	|  *** |
-	|  *** |	| *    |
-	+------+ ON	+------+ ON
-	  4321		  4321
-	(where the '*' indicates the position of the tab of the switch.)
-
-	When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x07ff_ffff	DDR		 128M
-	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
-	0xe000_0000	0xe00f_ffff	IMMR		 1M
-	0xe030_0000	0xe03f_ffff	PCI IO		 1M
-	0xe060_0000	0xe060_7fff	NAND FLASH (CS1) 32K
-	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
-
-	When booting from NAND, NAND flash is CS0 and NOR flash
-	is CS1.
-
-3.	Definitions
-
-3.1	Explanation of NEW definitions in:
-
-	include/configs/MPC8315ERDB.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC831x		MPC831x specific
-	CONFIG_MPC8315		MPC8315 specific
-	CONFIG_MPC8315ERDB	MPC8315ERDB board specific
-
-4.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
-	make all
-
-5.	Downloading and Flashing Images
-
-5.1	Reflash U-Boot Image using U-Boot
-
-	NOR flash:
-
-	tftp 40000 u-boot.bin
-	protect off all
-	erase fe000000 fe1fffff
-
-	cp.b 40000 fe000000 xxxx
-	protect on all
-
-	You have to supply the correct byte count with 'xxxx'
-	from the TFTP result log.
-
-	NAND flash:
-
-	=>tftpboot $loadaddr <filename>
-	=>nand erase 0 0x80000
-	=>nand write $loadaddr 0 0x80000
-
-	...where 0x80000 is the filesize rounded up to
-	the next 0x20000 increment.
-
-5.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
-	fdtfile, and bootfile).
-
-	Then, do one of the following, depending on whether you
-	want an NFS root or a ramdisk root:
-
-	=>run nfsboot
-	or
-	=>run ramboot
-
-6	Notes
-
-	The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
deleted file mode 100644
index e89d5d4955..0000000000
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *         Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static u8 read_board_info(void)
-{
-	u8 val8;
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
-		return val8;
-	else
-		return 0;
-}
-
-int checkboard(void)
-{
-	static const char * const rev_str[] = {
-		"0.0",
-		"0.1",
-		"1.0",
-		"1.1",
-		"<unknown>",
-	};
-	u8 info;
-	int i;
-
-	info = read_board_info();
-	i = (!info) ? 4: info & 0x03;
-
-	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
-
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
-{
-	const char disabled[] = "disabled";
-	const char *path;
-	int ret;
-
-	if (hwconfig_arg_cmp("board_type", "tsec1")) {
-		return;
-	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
-		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
-		       "        Assuming board with TSEC1.\n");
-		return;
-	}
-
-	ret = fdt_path_offset(fdt, "/aliases");
-	if (ret < 0) {
-		printf("WARNING: can't find /aliases node\n");
-		return;
-	}
-
-	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
-	if (!path) {
-		printf("WARNING: can't find ethernet0 alias\n");
-		return;
-	}
-
-	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	fsl_fdt_fixup_dr_usb(blob, bd);
-	fdt_tsec1_fixup(blob, bd);
-
-	return 0;
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
-	cpu_eth_init(bis);	/* Initialize TSECs first */
-	return pci_eth_init(bis);
-}
-
-#else /* CONFIG_NAND_SPL */
-
-int checkboard(void)
-{
-	puts("Board: Freescale MPC8315ERDB\n");
-	return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
-	board_early_init_f();
-	ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	timer_init();
-	dram_init();
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
-		      CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-
-#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
deleted file mode 100644
index ffbb79aaec..0000000000
--- a/board/freescale/mpc8315erdb/sdram.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Nick.Spence@freescale.com
- *          Wilson.Lo@freescale.com
- *          scottwood@freescale.com
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void resume_from_sleep(void)
-{
-	u32 magic = *(u32 *)0;
-
-	typedef void (*func_t)(void);
-	func_t resume = *(func_t *)4;
-
-	if (magic == 0xf5153ae5)
-		resume();
-
-	gd->flags &= ~GD_FLG_SILENT;
-	puts("\nResume from sleep failed: bad magic word\n");
-}
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-#ifndef CONFIG_SYS_RAMBOOT
-static long fixed_sdram(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
-	/*
-	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
-	 * or the DDR2 controller may fail to initialize correctly.
-	 */
-	__udelay(50000);
-
-	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Currently we use only one CS, so disable the other bank. */
-	im->ddr.cs_config[1] = 0;
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
-	else
-		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	sync();
-
-	return msize;
-}
-#else
-static long fixed_sdram(void)
-{
-	return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-int dram_init(void)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	u32 msize;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -ENXIO;
-
-	/* DDR SDRAM */
-	msize = fixed_sdram();
-
-	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		resume_from_sleep();
-
-	/* set total bus SDRAM size(bytes)  -- DDR */
-	gd->ram_size = msize;
-
-	return 0;
-}