diff options
author | Frieder Schrempf <frieder.schrempf@kontron.de> | 2022-08-24 16:59:13 +0300 |
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committer | Stefano Babic <sbabic@denx.de> | 2022-10-20 18:35:51 +0300 |
commit | 3a683aefdf523b9f32de2fe74ce82a9ce2476a2a (patch) | |
tree | 97b013540acee6f381f356fcc370df6ebca5e8c7 /board/kontron/sl-mx8mm/spl.c | |
parent | 8dd0924ea084cb3da608051a5047cb49701ab3c4 (diff) | |
download | u-boot-3a683aefdf523b9f32de2fe74ce82a9ce2476a2a.tar.xz |
imx: kontron-sl-mx8mm: Use new LPDDR4 config parameters
These parameters are needed for stable performance on new hardware
with Nanya LPDDR4 chips.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Diffstat (limited to 'board/kontron/sl-mx8mm/spl.c')
-rw-r--r-- | board/kontron/sl-mx8mm/spl.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 447da13984..affdc136e1 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -89,10 +89,10 @@ static void spl_dram_init(void) dram_timing.ddrc_cfg[2].val = 0xa1080020; dram_timing.ddrc_cfg[37].val = 0x1f; - dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110; - dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1; - dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110; - dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1; + dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x110; + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x1; + dram_timing.fsp_msg[1].fsp_cfg[9].val = 0x110; + dram_timing.fsp_msg[1].fsp_cfg[21].val = 0x1; dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110; dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1; |