diff options
| author | Michael Walle <michael@walle.cc> | 2022-05-31 00:02:09 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2022-06-20 10:52:45 +0300 |
| commit | 1029249b0065b32ae74e3fa7cd7d0f27d1b80efd (patch) | |
| tree | b7114b63ce167393219f0d005de5f93c48cd1b39 /board/kontron | |
| parent | 7fd5ca15019577418cdc058049fd9f814696014d (diff) | |
| download | u-boot-1029249b0065b32ae74e3fa7cd7d0f27d1b80efd.tar.xz | |
board: sl28: support 8 GiB memory
The board supports up to 8 GiB memory. The memory is soldered on the
board but the configuration is equivalent to a dual chip select, dual
rank DIMM module.
Signed-off-by: Michael Walle <michael@walle.cc>
Diffstat (limited to 'board/kontron')
| -rw-r--r-- | board/kontron/sl28/ddr.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index ed799c6e34..315d9f99c7 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -73,6 +73,13 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL; break; + case GPPORCR1_MEM_8GB_CS0_1: + dram_size = 0x200000000ULL; + ddr_cfg_regs.cs[0].bnds = 0x000000ff; + ddr_cfg_regs.cs[0].config = 0x80044403; + ddr_cfg_regs.cs[1].bnds = 0x010001ff; + ddr_cfg_regs.cs[1].config = 0x80044403; + break; case GPPORCR1_MEM_512MB_CS0: dram_size = 0x20000000; fallthrough; /* for now */ @@ -82,7 +89,6 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_2: dram_size = 0x100000000ULL; fallthrough; /* for now */ - case GPPORCR1_MEM_8GB_CS0_1: case GPPORCR1_MEM_8GB_CS0_1_2_3: dram_size = 0x200000000ULL; fallthrough; /* for now */ |