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author | Bibek Basu <bbasu@nvidia.com> | 2016-08-12 01:28:28 +0300 |
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committer | Tom Warren <twarren@nvidia.com> | 2016-08-15 20:26:14 +0300 |
commit | b064c9124acddbcdc70843f62fda13a2d7d7a392 (patch) | |
tree | b54a420cf982cbee21b87ae5c94b669a89726ecc /board/nvidia/venice2/as3722_init.c | |
parent | 027638d3cf6bf55996b50e41faccd51789a04eb0 (diff) | |
download | u-boot-b064c9124acddbcdc70843f62fda13a2d7d7a392.tar.xz |
ARM: tegra: set vdd_core for Jetson TK1
Program vdd_core for Jetson TK1 to 1V, which is the max safe voltage for
ultra low temperature operations. vdd_cpu and vdd_gpu are already at 1V.
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
(swarren: fixed comments to better match the code)
(swarren: moved board ifdef around data in header, made code generic)
(swarren: fixed typos in commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/nvidia/venice2/as3722_init.c')
-rw-r--r-- | board/nvidia/venice2/as3722_init.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 960fea7ee7..1770ec2468 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -32,7 +32,18 @@ void pmic_enable_cpu_vdd(void) { debug("%s entry\n", __func__); - /* Don't need to set up VDD_CORE - already done - by OTP */ +#ifdef AS3722_SD1VOLTAGE_DATA + /* Set up VDD_CORE, for boards where OTP is incorrect*/ + debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); + /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +#endif debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); /* |