diff options
author | Tianrui Wei <tianrui-wei@outlook.com> | 2021-07-01 07:54:19 +0300 |
---|---|---|
committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-07-06 08:50:56 +0300 |
commit | 8a44fe69439438797b93b2e7dd70e1a8fad31519 (patch) | |
tree | 327e92caeef61a85ca5c9fc1824673764736d59a /board/openpiton | |
parent | fe01f41d57b79d9ca94604503a25e55175744d42 (diff) | |
download | u-boot-8a44fe69439438797b93b2e7dd70e1a8fad31519.tar.xz |
board: riscv: add openpiton-riscv64 SoC support
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'board/openpiton')
-rw-r--r-- | board/openpiton/riscv64/Kconfig | 40 | ||||
-rw-r--r-- | board/openpiton/riscv64/MAINTAINERS | 8 | ||||
-rw-r--r-- | board/openpiton/riscv64/Makefile | 5 | ||||
-rw-r--r-- | board/openpiton/riscv64/openpiton-riscv64.c | 33 |
4 files changed, 86 insertions, 0 deletions
diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig new file mode 100644 index 0000000000..193c890046 --- /dev/null +++ b/board/openpiton/riscv64/Kconfig @@ -0,0 +1,40 @@ +if TARGET_OPENPITON_RISCV64 + +config SYS_BOARD + default "riscv64" + +config SYS_VENDOR + default "openpiton" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "openpiton-riscv64" + +config SYS_TEXT_BASE + default 0x81000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x81000000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x82000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU_RISCV + imply RISCV_TIMER + imply SPL_SIFIVE_CLINT + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_SMP + imply SPL_MMC + imply SMP + imply SPL_RISCV_MMODE + +endif diff --git a/board/openpiton/riscv64/MAINTAINERS b/board/openpiton/riscv64/MAINTAINERS new file mode 100644 index 0000000000..f91c000c83 --- /dev/null +++ b/board/openpiton/riscv64/MAINTAINERS @@ -0,0 +1,8 @@ +Openpiton BOARD +M: Tianrui Wei<tianrui-wei@outlook.com> +S: Maintained +F: board/openpiton/riscv64/ +F: include/configs/openpiton-riscv64.h +F: configs/openpiton_riscv64_defconfig +F: configs/openpiton_riscv64_spl_defconfig +F: drivers/mmc/piton_mmc.c diff --git a/board/openpiton/riscv64/Makefile b/board/openpiton/riscv64/Makefile new file mode 100644 index 0000000000..3bffa75a9a --- /dev/null +++ b/board/openpiton/riscv64/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Tianrui Wei +# Tianrui Wei <tianrui-wei@outlook.com> +obj-y += openpiton-riscv64.o diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c new file mode 100644 index 0000000000..f2282d1548 --- /dev/null +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * Copyright (c) 2021 Tianrui Wei + * + * + * Authors: + * Pragnesh Patel <pragnesh.patel@sifive.com> + * Tianrui Wei <tianrui-wei@outlook.com> + */ +#include <common.h> +#include <init.h> +#include <configs/openpiton-riscv64.h> +#include <dm.h> +#include <spl.h> + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { + BOOT_DEVICE_MMC1, + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +int board_init(void) +{ + return 0; +} |