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| author | Matwey V. Kornilov <matwey.kornilov@gmail.com> | 2022-08-11 17:18:12 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-20 23:40:14 +0300 |
| commit | 297c439b37b158911718c47d7027c354e4988174 (patch) | |
| tree | 505edf0e7963ccea29f7c01aee11b49211b74134 /board/phytec/phycore_am335x_r2 | |
| parent | 9ca6c91732533c4d8e809dac9f602c28ae4923cc (diff) | |
| download | u-boot-297c439b37b158911718c47d7027c354e4988174.tar.xz | |
Restore pcm051_rev3_defconfig config
pcm051_rev3_defconfig config (Phytec Wega board) has been dropped in
64efd11d ("arm: Remove pcm051 board")
due to expired migration deadlines. Here, pcm051_rev3_defconfig support is
reintroduced.
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/phytec/phycore_am335x_r2')
| -rw-r--r-- | board/phytec/phycore_am335x_r2/Kconfig | 2 | ||||
| -rw-r--r-- | board/phytec/phycore_am335x_r2/MAINTAINERS | 5 | ||||
| -rw-r--r-- | board/phytec/phycore_am335x_r2/board.c | 26 |
3 files changed, 32 insertions, 1 deletions
diff --git a/board/phytec/phycore_am335x_r2/Kconfig b/board/phytec/phycore_am335x_r2/Kconfig index 77055e043c..4183c2410e 100644 --- a/board/phytec/phycore_am335x_r2/Kconfig +++ b/board/phytec/phycore_am335x_r2/Kconfig @@ -1,4 +1,4 @@ -if TARGET_PHYCORE_AM335X_R2 +if TARGET_PCM051 || TARGET_PHYCORE_AM335X_R2 config SYS_BOARD default "phycore_am335x_r2" diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS index 8d02b0e198..28c69cb1a8 100644 --- a/board/phytec/phycore_am335x_r2/MAINTAINERS +++ b/board/phytec/phycore_am335x_r2/MAINTAINERS @@ -9,3 +9,8 @@ F: board/phytec/phycore_am335x_r2 F: include/configs/phycore_am335x_r2.h F: configs/phycore-am335x-r2-regor_defconfig F: configs/phycore-am335x-r2-wega_defconfig + +phyCORE AM335x R3 WEGA BOARD +M: Matwey V. Kornilov <matwey.kornilov@gmail.com> +S: Maintained +F: configs/pcm051_rev3_defconfig diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index 5ca9415204..d97ebd0151 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -31,7 +31,11 @@ DECLARE_GLOBAL_DATA_PTR; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* DDR RAM defines */ +#if defined(CONFIG_TARGET_PCM051) +#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ +#else #define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */ +#endif #define OSC (V_OSCK / 1000000) const struct dpll_params dpll_ddr = { @@ -65,6 +69,7 @@ enum { PHYCORE_R2_MT41K128M16JT_256MB, PHYCORE_R2_MT41K256M16TW107IT_512MB, PHYCORE_R2_MT41K512M16HA125IT_1024MB, + PHYCORE_R13_MT41K256M16HA125E_256MB, }; struct am335x_sdram_timings { @@ -127,10 +132,30 @@ static struct am335x_sdram_timings physom_timings[] = { .datawrsratio0 = 0x82, }, }, + [PHYCORE_R13_MT41K256M16HA125E_256MB] = { + .ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, + }, + .ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, + }, + }, }; void sdram_init(void) { +#if defined(CONFIG_TARGET_PCM051) + int ram_type_index = PHYCORE_R13_MT41K256M16HA125E_256MB; +#else /* Configure memory to maximum supported size for detection */ int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB; @@ -157,6 +182,7 @@ void sdram_init(void) ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB; break; } +#endif config_ddr(DDR_CLK_MHZ, &ioregs, &physom_timings[ram_type_index].ddr3_data, &ddr3_cmd_ctrl_data, |