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| author | Teresa Remmet <t.remmet@phytec.de> | 2021-07-07 15:58:02 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-07-10 17:53:34 +0300 |
| commit | fd82763cd256a0470d85a00458735721db719a00 (patch) | |
| tree | 6df8c87f4055cd4a9c30bc8ea52c29a0f1c09d2c /board/phytec | |
| parent | 0f166b85ac473f72aaff6489f880d26cc41a1148 (diff) | |
| download | u-boot-fd82763cd256a0470d85a00458735721db719a00.tar.xz | |
board: phytec: phycore-imx8mp: Enable DVS1 control
Enable DVS1 control through PMIC_STBY_REQ.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/phycore_imx8mp/spl.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 815ca9badc..19c486e551 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -66,7 +66,11 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); - /* set WDOG_B_CFG to cold reset */ + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); return 0; |