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author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-04-26 14:31:39 +0300 |
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committer | Marek Vasut <marex@denx.de> | 2018-06-01 10:47:21 +0300 |
commit | 63e22517a39046d62b86ebf0f7fe6e0db575f339 (patch) | |
tree | 2e2a7eef8d9ca9b07a0fa7669e285dbe1916d380 /board/renesas/ebisu/ebisu.c | |
parent | 031fa18f70c38fe53a90f6ab4a1a441bf1a78280 (diff) | |
download | u-boot-63e22517a39046d62b86ebf0f7fe6e0db575f339.tar.xz |
ARM: renesas: Add R8A77990 E3 Ebisu board
Add support for the R8A77990 Ebisu board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/ebisu/ebisu.c')
-rw-r--r-- | board/renesas/ebisu/ebisu.c | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c new file mode 100644 index 0000000000..92062141a2 --- /dev/null +++ b/board/renesas/ebisu/ebisu.c @@ -0,0 +1,87 @@ +/* + * board/renesas/ebisu/ebisu.c + * This file is Ebisu board support. + * + * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) +{ +} + +#define TMU0_MSTP125 BIT(25) /* secure */ + +int board_early_init_f(void) +{ + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(ulong addr) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} |