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| author | Andy Hu <andy.hu@starfivetech.com> | 2023-03-08 12:32:09 +0300 |
|---|---|---|
| committer | Andy Hu <andy.hu@starfivetech.com> | 2023-05-18 16:08:24 +0300 |
| commit | fffd811e3d69b7cdd6118ddeb7ab8354f6ea2bfa (patch) | |
| tree | b5ab9a15135b57ed0eb300906fa1a66c2633a17f /board/sagem | |
| parent | 040cfd685cc90a3b93abf4b035589752ea18f113 (diff) | |
| download | u-boot-fffd811e3d69b7cdd6118ddeb7ab8354f6ea2bfa.tar.xz | |
riscv: dts: starfive: add zicsr_zifencei to riscv,isa string
Starting from gcc 12.x, csr and fence instructions have been
separated from the base I instruction set. special the
zicsr_zifencei string to DT riscv,isa string
Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
Diffstat (limited to 'board/sagem')
0 files changed, 0 insertions, 0 deletions