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author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2020-05-29 09:44:51 +0300 |
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committer | Andes <uboot@andestech.com> | 2020-07-03 10:09:06 +0300 |
commit | 5ce50206ed24080707946849d3542534fadf8cbf (patch) | |
tree | 291e2af14db172b24773bc1a8c7c2b699b263d29 /board/sifive | |
parent | edf4fc2bafac18399d07152be51cb77d5d1bb3ac (diff) | |
download | u-boot-5ce50206ed24080707946849d3542534fadf8cbf.tar.xz |
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'board/sifive')
-rw-r--r-- | board/sifive/fu540/fu540.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index fa705dea71..27ff52f903 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -15,6 +15,7 @@ #include <linux/io.h> #include <misc.h> #include <spl.h> +#include <asm/arch/cache.h> /* * This define is a value used for error/unknown serial. @@ -114,7 +115,14 @@ int misc_init_r(void) int board_init(void) { - /* For now nothing to do here. */ + int ret; + + /* enable all cache ways */ + ret = cache_enable_ways(); + if (ret) { + debug("%s: could not enable cache ways\n", __func__); + return ret; + } return 0; } |