board: synquacer: Add DeveloperBox 96boards EE support

Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.

For more information, see this page;
  https://www.96boards.org/product/developerbox/

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>

1 files changed, 146 insertions, 0 deletions

diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
new file mode 100644
index 0000000000..34335baec3
--- /dev/null
+++ b/board/socionext/developerbox/developerbox.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * u-boot/board/socionext/developerbox/developerbox.c
+ *
+ * Copyright (C) 2016-2017 Socionext Inc.
+ * Copyright (C) 2021 Linaro Ltd.
+ */
+#include <asm/types.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env_internal.h>
+#include <fdt_support.h>
+#include <log.h>
+
+static struct mm_region sc2a11_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* 1st DDR block */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = PHYS_SDRAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* 2nd DDR place holder */
+		0,
+	}, {
+		/* 3rd DDR place holder */
+		0,
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = sc2a11_mem_map;
+
+#define DDR_REGION_INDEX(i)	(1 + (i))
+#define MAX_DDR_REGIONS		3
+
+struct draminfo_entry {
+	u64	base;
+	u64	size;
+};
+
+struct draminfo {
+	u32	nr_regions;
+	u32	reserved;
+	struct draminfo_entry	entry[3];
+};
+
+struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+	gd->env_addr = (ulong)&default_environment[0];
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
+	fdt_del_node_and_alias(blob, "spi_nor");
+	fdt_del_node_and_alias(blob, "i2c0");
+
+	return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+
+int dram_init(void)
+{
+	struct draminfo_entry *ent = synquacer_draminfo->entry;
+	struct mm_region *mr;
+	int i, ri;
+
+	if (synquacer_draminfo->nr_regions < 1) {
+		log_err("Failed to get correct DRAM information\n");
+		return -1;
+	}
+
+	/*
+	 * U-Boot RAM size must be under the first DRAM region so that it doesn't
+	 * access secure memory which is at the end of the first DRAM region.
+	 */
+	gd->ram_size = ent[0].size;
+
+	/* Update memory region maps */
+	for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
+		if (i >= MAX_DDR_REGIONS)
+			break;
+
+		ri = DDR_REGION_INDEX(i);
+		mem_map[ri].phys = ent[i].base;
+		mem_map[ri].size = ent[i].size;
+		if (i == 0)
+			continue;
+
+		mr = &mem_map[DDR_REGION_INDEX(0)];
+		mem_map[ri].virt = mr->virt + mr->size;
+		mem_map[ri].attrs = mr->attrs;
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	struct draminfo_entry *ent = synquacer_draminfo->entry;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+		if (i < synquacer_draminfo->nr_regions) {
+			debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
+			gd->bd->bi_dram[i].start = ent[i].base;
+			gd->bd->bi_dram[i].size = ent[i].size;
+		}
+	}
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   SC2A11:Cortex-A53 MPCore 24cores\n");
+	return 0;
+}