diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-18 04:22:26 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:36 +0300 |
| commit | c43d28132317bd745a485543569e80d4bcfee018 (patch) | |
| tree | 50ab2423762b17dedc2030439f76f8e811c5a845 /board/starfive/evb | |
| parent | 8a8168dd0c8404a6c3d72a924b7b4195c1cde8fb (diff) | |
| download | u-boot-c43d28132317bd745a485543569e80d4bcfee018.tar.xz | |
SPL:riscv:starfive-jh7110: Adjust CPU working frequency
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'board/starfive/evb')
| -rw-r--r-- | board/starfive/evb/spl.c | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c index 21ce5d12c1..5b2b397508 100644 --- a/board/starfive/evb/spl.c +++ b/board/starfive/evb/spl.c @@ -58,10 +58,43 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR); } +/* set PLL0 output to 1.5GHz*/ +__maybe_unused static void spl_cpu_fre_150(void) +{ + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK, + BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK, + BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK, + BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK, + (125 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK, + BIT(PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK); +} + +/* set PLL0 output to 1.25GHz*/ +static void spl_cpu_fre_125(void) +{ + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK, + BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK, + BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK, + BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK, + (52 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK); + clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK, + (0 << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK); +} + + void board_init_f(ulong dummy) { int ret; + spl_cpu_fre_125(); + /*DDR control depend clk init*/ clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK, BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK); @@ -81,7 +114,7 @@ void board_init_f(ulong dummy) clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET, CLK_QSPI_REF_SW_MASK, - BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK); + (0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK); /*set GPIO to 1.8v*/ setbits_be32(SYS_SYSCON_BASE + 0xC, 0xf); |