diff options
author | Marek Vasut <marek.vasut@gmail.com> | 2020-04-29 21:09:08 +0300 |
---|---|---|
committer | Stefano Babic <sbabic@denx.de> | 2020-05-10 14:19:39 +0300 |
commit | b52fb0b0b5da80a059ba982139401e57ac4e9a2e (patch) | |
tree | af23659cb13dffc1155842f9a05be4e109e4c788 /board/technexion/pico-imx8mq/pico-imx8mq.c | |
parent | b77d0292ca9f3ca69259dca7e2c5e193a403b289 (diff) | |
download | u-boot-b52fb0b0b5da80a059ba982139401e57ac4e9a2e.tar.xz |
ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQ
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier
board. Currently working is ethernet, serial, eMMC. DT is imported
from Linux 5.4.28 ("462afcd6e7ea") .
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/technexion/pico-imx8mq/pico-imx8mq.c')
-rw-r--r-- | board/technexion/pico-imx8mq/pico-imx8mq.c | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c new file mode 100644 index 0000000000..822357bb12 --- /dev/null +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <malloc.h> +#include <errno.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/clock.h> +#include <spl.h> +#include <power/pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +int dram_init(void) +{ + int ddr_size = readl(M4_BOOTROM_BASE_ADDR); + + if (ddr_size == 0x4) + gd->ram_size = 0x100000000; + else if (ddr_size == 0x3) + gd->ram_size = 0xc0000000; + else if (ddr_size == 0x2) + gd->ram_size = 0x80000000; + else if (ddr_size == 0x1) + gd->ram_size = 0x40000000; + else + printf("Unknown DDR type!!!\n"); + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size -= rom_pointer[1]; + + return 0; +} + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +#define FEC_PWR_PAD IMX_GPIO_NR(1, 0) +static iomux_v3_cfg_t const fec1_pads[] = { + /* Reset */ + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Power */ + IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr"); + gpio_direction_output(IMX_GPIO_NR(1, 0), 1); + udelay(500); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_rev", "iMX8MQ"); +#endif + return 0; +} |