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authorNeha Malcom Francis <n-francis@ti.com>2023-07-21 21:44:30 +0300
committerTom Rini <trini@konsulko.com>2023-07-22 02:36:58 +0300
commitca5f1e25e5cb1caacac3dc5ef6fb3bf00dbf9d30 (patch)
tree35b3b4e261c8a9ac521acff238b69623a17ed41f /board/ti/j721e
parente6135b061430432265943a9a58241b9a5aecfb27 (diff)
downloadu-boot-ca5f1e25e5cb1caacac3dc5ef6fb3bf00dbf9d30.tar.xz
j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j7200-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J7200 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Diffstat (limited to 'board/ti/j721e')
-rw-r--r--board/ti/j721e/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 4a127c4a10..e6cb21f77b 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -33,6 +33,7 @@ config TARGET_J7200_A72_EVM
select BOARD_LATE_INIT
imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
config TARGET_J7200_R5_EVM
bool "TI K3 based J7200 EVM running on R5"
@@ -42,6 +43,7 @@ config TARGET_J7200_R5_EVM
select RAM
select SPL_RAM
select K3_DDRSS
+ select BINMAN
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT