board: ti: k2g: Add support for K2G ICE with 1GHz Silicon

Add board detection support for K2G ICE with FlagChip 1GHz silicon.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

5 files changed, 17 insertions, 6 deletions

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index c7be540028..53bc12791d 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -48,11 +48,11 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
-	if (!board_is_k2g_ice())
+	if (!(board_is_k2g_ice() || board_is_k2g_i1()))
 		aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
 #endif
 
-	if (!board_is_k2g_ice()) {
+	if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
 		if (ddr3_size)
 			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
 		else
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index d0cfbf5a75..93fc3887f4 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -25,6 +25,10 @@ static inline int board_is_k2g_ice(void)
 {
 	return board_ti_is("66AK2GIC");
 }
+static inline int board_is_k2g_i1(void)
+{
+	return board_ti_is("66AK2GI1");
+}
 #else
 static inline int board_is_k2g_gp(void)
 {
@@ -34,6 +38,10 @@ static inline int board_is_k2g_ice(void)
 {
 	return false;
 }
+static inline int board_is_k2g_i1(void)
+{
+	return false;
+}
 #endif
 
 void spl_init_keystone_plls(void);
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index a71024bcbc..2be86d6d26 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -248,7 +248,8 @@ int board_fit_config_name_match(const char *name)
 	else if (!strcmp(name, "keystone-k2g-evm") &&
 		(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
 		return 0;
-	else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
+	else if (!strcmp(name, "keystone-k2g-ice") &&
+		 (board_ti_is("66AK2GIC") || board_is_k2g_i1()))
 		return 0;
 	else
 		return -1;
@@ -322,7 +323,7 @@ int embedded_dtb_select(void)
 			     BIT(9));
 		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 			     BIT(9));
-	} else if (board_is_k2g_ice()) {
+	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
 		/* GBE Phy workaround. For Phy to latch the input
 		 * configuration, a GPIO reset is asserted at the
 		 * Phy reset pin to latch configuration correctly after SoC
@@ -364,6 +365,8 @@ int board_late_init(void)
 		env_set("board_name", "66AK2GG1\0");
 	else if (board_is_k2g_ice())
 		env_set("board_name", "66AK2GIC\0");
+	else if (board_is_k2g_i1())
+		env_set("board_name", "66AK2GI1\0");
 #endif
 	return 0;
 }
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 563c5e9950..3000d7245e 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -174,7 +174,7 @@ u32 ddr3_init(void)
 	} else if (board_is_k2g_gp()) {
 		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
 		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
-	} else if (board_is_k2g_ice()) {
+	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
 		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
 		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
 	}
diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
index 3ecf571c5c..fa6c92cbdf 100644
--- a/board/ti/ks2_evm/mux-k2g.h
+++ b/board/ti/ks2_evm/mux-k2g.h
@@ -377,7 +377,7 @@ void k2g_mux_config(void)
 		configure_pin_mux(k2g_generic_pin_cfg);
 	} else if (board_is_k2g_gp() || board_is_k2g_g1()) {
 		configure_pin_mux(k2g_evm_pin_cfg);
-	} else if (board_is_k2g_ice()) {
+	} else if (board_is_k2g_ice() || board_is_k2g_i1()) {
 		configure_pin_mux(k2g_ice_evm_pin_cfg);
 	} else {
 		puts("Unknown board, cannot configure pinmux.");