ppc: Remove xpedite boards

These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove them.  As this includes
the last ARCH_MPC8572 platform, remove that as well.

Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>

28 files changed, 0 insertions, 1338 deletions

diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index b5c6900021..4932030547 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -4,7 +4,6 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
-obj-$(CONFIG_ARCH_MPC8572)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_ARCH_P2020)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
diff --git a/board/xes/xpedite517x/Kconfig b/board/xes/xpedite517x/Kconfig
deleted file mode 100644
index 91bbd22451..0000000000
--- a/board/xes/xpedite517x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE517X
-
-config SYS_BOARD
-	default "xpedite517x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite517x"
-
-endif
diff --git a/board/xes/xpedite517x/MAINTAINERS b/board/xes/xpedite517x/MAINTAINERS
deleted file mode 100644
index 26e0acccb0..0000000000
--- a/board/xes/xpedite517x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE517X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite517x/
-F:	include/configs/xpedite517x.h
-F:	configs/xpedite517x_defconfig
diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile
deleted file mode 100644
index 10ac76a37a..0000000000
--- a/board/xes/xpedite517x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= xpedite517x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
deleted file mode 100644
index a3fd2fc8ca..0000000000
--- a/board/xes/xpedite517x/ddr.c
+++ /dev/null
@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <log.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork.  These are:
- *   1.) CPO (Read Capture Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths and
- *                   chip-specific internal delays.
- *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths.
- *                   Unless clock and DQ lanes are very different
- *                   lengths (>2"), this should be set to the nominal value
- *                   of 1/2 clock delay.
- *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *           - DDR_SDRAM_CLK_CNTL register
- *           Source: Signal Integrity Simulations
- *   4.) 2T Timing on Addr/Ctl
- *           - TIMING_CFG_2 register
- *           Source: Signal Integrity Simulations
- *           Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     PCB routing on the XPedite5170 is nearly identical to the XPedite5370
- *     so we use the XPedite5370 settings as a basis for the XPedite5170.
- */
-
-typedef struct board_memctl_options {
-	uint16_t datarate_mhz_low;
-	uint16_t datarate_mhz_high;
-	uint8_t clk_adjust;
-	uint8_t cpo_override;
-	uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 9,
-			.write_data_delay	= 2,
-		},
-	},
-	{
-		/* Controller 1 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 7,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			dimm_params_t *pdimm,
-			unsigned int ctrl_num)
-{
-	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
-	sys_info_t sysinfo;
-	int i;
-	unsigned int datarate;
-
-	get_sys_info(&sysinfo);
-	datarate = get_ddr_freq(0) / 1000000;
-
-	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
-		if ((bopts[i].datarate_mhz_low <= datarate) &&
-		    (bopts[i].datarate_mhz_high >= datarate)) {
-			debug("controller %d:\n", ctrl_num);
-			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
-			debug(" cpo = %d\n", bopts[i].cpo_override);
-			debug(" write_data_delay = %d\n",
-				bopts[i].write_data_delay);
-			popts->clk_adjust = bopts[i].clk_adjust;
-			popts->cpo_override = bopts[i].cpo_override;
-			popts->write_data_delay = bopts[i].write_data_delay;
-		}
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c
deleted file mode 100644
index b82f9f0d3b..0000000000
--- a/board/xes/xpedite517x/law.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE
-	/* NAND LAW covers 2 NAND flashes */
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
deleted file mode 100644
index 8a5b52c495..0000000000
--- a/board/xes/xpedite517x/xpedite517x.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-#include "../common/fsl_8xxx_misc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-#endif
-
-/*
- * Print out which flash was booted from and if booting from the 2nd flash,
- * swap flash chip selects to maintain consistent flash numbering/addresses.
- */
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size = fsl_ddr_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/* Initialize and enable DDR ECC */
-	ddr_enable_ecc(dram_size);
-#endif
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/xes/xpedite520x/Kconfig b/board/xes/xpedite520x/Kconfig
deleted file mode 100644
index 9c0c2461fd..0000000000
--- a/board/xes/xpedite520x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE520X
-
-config SYS_BOARD
-	default "xpedite520x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite520x"
-
-endif
diff --git a/board/xes/xpedite520x/MAINTAINERS b/board/xes/xpedite520x/MAINTAINERS
deleted file mode 100644
index f7bd437cc6..0000000000
--- a/board/xes/xpedite520x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE520X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite520x/
-F:	include/configs/xpedite520x.h
-F:	configs/xpedite520x_defconfig
diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile
deleted file mode 100644
index 12e75da5b3..0000000000
--- a/board/xes/xpedite520x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= xpedite520x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
deleted file mode 100644
index c142bec406..0000000000
--- a/board/xes/xpedite520x/ddr.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
-{
-	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
-
-	/* We use soldered memory, but use an SPD EEPROM to describe it.
-	 * The SPD has an unspecified dimm type, but the DDR2 initialization
-	 * code requires a specific type to be specified. This sets the type
-	 * as a standard unregistered SO-DIMM. */
-	if (spd->dimm_type == 0) {
-		spd->dimm_type = 0x4;
-		((uchar *)spd)[63] += 0x4;
-	}
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 9;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
deleted file mode 100644
index 10613ead3f..0000000000
--- a/board/xes/xpedite520x/law.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite520x/tlb.c b/board/xes/xpedite520x/tlb.c
deleted file mode 100644
index d45f532861..0000000000
--- a/board/xes/xpedite520x/tlb.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if CONFIG_PCI1
-	/* *I*G* - PCI MEM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 3, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#if CONFIG_PCI2
-	/* *I*G* - PCI MEM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
-	/* *I*G* - PCI IO */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_16M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c
deleted file mode 100644
index 63e1e0efe5..0000000000
--- a/board/xes/xpedite520x/xpedite520x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/xes/xpedite537x/Kconfig b/board/xes/xpedite537x/Kconfig
deleted file mode 100644
index 35b3917a6d..0000000000
--- a/board/xes/xpedite537x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE537X
-
-config SYS_BOARD
-	default "xpedite537x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite537x"
-
-endif
diff --git a/board/xes/xpedite537x/MAINTAINERS b/board/xes/xpedite537x/MAINTAINERS
deleted file mode 100644
index b6123acc0f..0000000000
--- a/board/xes/xpedite537x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE537X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite537x/
-F:	include/configs/xpedite537x.h
-F:	configs/xpedite537x_defconfig
diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile
deleted file mode 100644
index 82575cf05e..0000000000
--- a/board/xes/xpedite537x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= xpedite537x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
deleted file mode 100644
index f55102a072..0000000000
--- a/board/xes/xpedite537x/ddr.c
+++ /dev/null
@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <log.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		 sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork.  These are:
- *   1.) CPO (Read Capture Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths and
- *                   chip-specific internal delays.
- *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- *           - TIMING_CFG_2 register
- *           Source: Calculation based on board trace lengths.
- *                   Unless clock and DQ lanes are very different
- *                   lengths (>2"), this should be set to the nominal value
- *                   of 1/2 clock delay.
- *   3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *           - DDR_SDRAM_CLK_CNTL register
- *           Source: Signal Integrity Simulations
- *   4.) 2T Timing on Addr/Ctl
- *           - TIMING_CFG_2 register
- *           Source: Signal Integrity Simulations
- *           Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     ====== XPedite5370 DDR2-600 read delay calculations ======
- *
- *     See Freescale's App Note AN2583 as refrence.  This document also
- *     contains the chip-specific delays for 8548E, 8572, etc.
- *
- *     For MPC8572E
- *     Minimum chip delay (Ch 0): 1.372ns
- *     Maximum chip delay (Ch 0): 2.914ns
- *     Minimum chip delay (Ch 1): 1.220ns
- *     Maximum chip delay (Ch 1): 2.595ns
- *
- *     CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
- *
- *     Minimum delay calc (Ch 0):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     2.3" * 180 - 400ps     + 1.9" * 180         + 2080ps     + 1372ps
- *                                                 = 3808ps
- *                                                 = 3.808ns
- *
- *     Maximum delay calc (Ch 0):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- *     2.3" * 180 + 400ps     + 2.4" * 180         + 2080ps     + 2914ps
- *                                                 = 6240ps
- *                                                 = 6.240ns
- *
- *     Minimum delay calc (Ch 1):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180- 400ps     + 0.7" * 180         + 2080ps     + 1220ps
- *                                                 = 3288ps
- *                                                 = 3.288ns
- *
- *     Maximum delay calc (Ch 1):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180+ 400ps     + 1.1" * 180         + 2080ps     + 2595ps
- *                                                 = 5536ps
- *                                                 = 5.536ns
- *
- *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
- *              This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
- *              This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
- *
- *
- *     ====== XPedite5370 DDR2-800 read delay calculations ======
- *
- *     See Freescale's App Note AN2583 as refrence.  This document also
- *     contains the chip-specific delays for 8548E, 8572, etc.
- *
- *     For MPC8572E
- *     Minimum chip delay (Ch 0): 1.372ns
- *     Maximum chip delay (Ch 0): 2.914ns
- *     Minimum chip delay (Ch 1): 1.220ns
- *     Maximum chip delay (Ch 1): 2.595ns
- *
- *     CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
- *
- *     Minimum delay calc (Ch 0):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     2.3" * 180 - 350ps     + 1.9" * 180         + 1563ps     + 1372ps
- *                                                 = 3341ps
- *                                                 = 3.341ns
- *
- *     Maximum delay calc (Ch 0):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- *     2.3" * 180 + 350ps     + 2.4" * 180         + 1563ps     + 2914ps
- *                                                 = 5673ps
- *                                                 = 5.673ns
- *
- *     Minimum delay calc (Ch 1):
- *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180- 350ps     + 0.7" * 180         + 1563ps     + 1220ps
- *                                                 = 2822ps
- *                                                 = 2.822ns
- *
- *     Maximum delay calc (Ch 1):
- *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- *     1.46" * 180+ 350ps     + 1.1" * 180         + 1563ps     + 2595ps
- *                                                 = 4968ps
- *                                                 = 4.968ns
- *
- *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
- *              This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
- *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
- *              This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- *
- * Write latency (WR_DATA_DELAY) is calculated by doing the following:
- *
- *      The DDR SDRAM specification requires DQS be received no sooner than
- *      75% of an SDRAM clock period—and no later than 125% of a clock
- *      period—from the capturing clock edge of the command/address at the
- *      SDRAM.
- *
- * Based on the above tracelengths, the following are calculated:
- *      Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 =  0.342ns
- *      Ch. 0 8572 to DRAM propagation (CLKs) :     2.3" * 180 =  0.414ns
- *      Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 =  0.126ns
- *      Ch. 1 8572 to DRAM propagation (CLKs   ) : 1.47" * 180 =  0.264ns
- *
- * Difference in arrival time CLK vs. DQS:
- *      Ch. 0 0.072ns
- *      Ch. 1 0.138ns
- *
- *      Both of these values are much less than 25% of the clock
- *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
- *      the 1/2 cycle which normally aligns the first DQS transition
- *      exactly WL (CAS latency minus one cycle) after the CAS strobe.
- *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
- *      terminology corresponds to exactly one clock period delay after
- *      the CAS strobe. (due to the fact that the "delay" is referenced
- *      from the *falling* edge of the CLK, just after the rising edge
- *      which the CAS strobe is latched on.
- */
-
-typedef struct board_memctl_options {
-	uint16_t datarate_mhz_low;
-	uint16_t datarate_mhz_high;
-	uint8_t clk_adjust;
-	uint8_t cpo_override;
-	uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 9,
-			.write_data_delay	= 2,
-		},
-	},
-	{
-		/* Controller 1 */
-		{
-			/* DDR2 600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo_override		= 7,
-			.write_data_delay	= 2,
-		},
-		{
-			/* DDR2 800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo_override		= 8,
-			.write_data_delay	= 2,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			   dimm_params_t *pdimm,
-			   unsigned int ctrl_num)
-{
-	struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
-	sys_info_t sysinfo;
-	int i;
-	unsigned int datarate;
-
-	get_sys_info(&sysinfo);
-	datarate = sysinfo.freq_ddrbus / 1000 / 1000;
-
-	for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
-		if ((bopts[i].datarate_mhz_low <= datarate) &&
-		    (bopts[i].datarate_mhz_high >= datarate)) {
-			debug("controller %d:\n", ctrl_num);
-			debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
-			debug(" cpo = %d\n", bopts[i].cpo_override);
-			debug(" write_data_delay = %d\n",
-			      bopts[i].write_data_delay);
-			popts->clk_adjust = bopts[i].clk_adjust;
-			popts->cpo_override = bopts[i].cpo_override;
-			popts->write_data_delay = bopts[i].write_data_delay;
-		}
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c
deleted file mode 100644
index a1f375900c..0000000000
--- a/board/xes/xpedite537x/law.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite537x/tlb.c b/board/xes/xpedite537x/tlb.c
deleted file mode 100644
index 6d50360f06..0000000000
--- a/board/xes/xpedite537x/tlb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-	/* **M** - Boot page for secondary processors */
-	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c
deleted file mode 100644
index 437b57d4ff..0000000000
--- a/board/xes/xpedite537x/xpedite537x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/xes/xpedite550x/Kconfig b/board/xes/xpedite550x/Kconfig
deleted file mode 100644
index 1b00137a48..0000000000
--- a/board/xes/xpedite550x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE550X
-
-config SYS_BOARD
-	default "xpedite550x"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite550x"
-
-endif
diff --git a/board/xes/xpedite550x/MAINTAINERS b/board/xes/xpedite550x/MAINTAINERS
deleted file mode 100644
index 017f368757..0000000000
--- a/board/xes/xpedite550x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE550X BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite550x/
-F:	include/configs/xpedite550x.h
-F:	configs/xpedite550x_defconfig
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
deleted file mode 100644
index 1aacb375cc..0000000000
--- a/board/xes/xpedite550x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007-2008 Freescale Semiconductor, Inc.
-
-obj-y	+= xpedite550x.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
deleted file mode 100644
index ad52c9455b..0000000000
--- a/board/xes/xpedite550x/ddr.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
-{
-	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
-		 sizeof(ddr3_spd_eeprom_t));
-}
-
-/*
- *     There are traditionally three board-specific SDRAM timing parameters
- *     which must be calculated based on the particular PCB artwork.  These are:
- *     1.) CPO (Read Capture Delay)
- *	       - TIMING_CFG_2 register
- *	       Source: Calculation based on board trace lengths and
- *		       chip-specific internal delays.
- *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *	       - DDR_SDRAM_CLK_CNTL register
- *	       Source: Signal Integrity Simulations
- *     3.) 2T Timing on Addr/Ctl
- *	       - TIMING_CFG_2 register
- *	       Source: Signal Integrity Simulations
- *	       Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- *     ====== XPedite550x DDR3-800 read delay calculations ======
- *
- *     The P2020 processor provides an autoleveling option. Setting CPO to
- *     0x1f enables this auto configuration.
- */
-
-typedef struct {
-	unsigned short datarate_mhz_low;
-	unsigned short datarate_mhz_high;
-	unsigned char clk_adjust;
-	unsigned char cpo;
-} board_specific_parameters_t;
-
-const board_specific_parameters_t board_specific_parameters[][20] = {
-	{
-		/* Controller 0 */
-		{
-			/* DDR3-600/667 */
-			.datarate_mhz_low	= 500,
-			.datarate_mhz_high	= 750,
-			.clk_adjust		= 5,
-			.cpo			= 31,
-		},
-		{
-			/* DDR3-800 */
-			.datarate_mhz_low	= 750,
-			.datarate_mhz_high	= 850,
-			.clk_adjust		= 5,
-			.cpo			= 31,
-		},
-	},
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const board_specific_parameters_t *pbsp =
-				&(board_specific_parameters[ctrl_num][0]);
-	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
-				sizeof(board_specific_parameters[0][0]);
-	u32 i;
-	ulong ddr_freq;
-
-	/*
-	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
-	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
-	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
-	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
-	 */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
-			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 0;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 4;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-				popts->cs_local_opts[i].odt_rd_cfg = 3;
-				popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
-	}
-
-	/*
-	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-
-	for (i = 0; i < num_params; i++) {
-		if (ddr_freq >= pbsp->datarate_mhz_low &&
-		    ddr_freq <= pbsp->datarate_mhz_high) {
-			popts->clk_adjust = pbsp->clk_adjust;
-			popts->cpo_override = pbsp->cpo;
-			popts->twot_en = 0;
-			break;
-		}
-		pbsp++;
-	}
-
-	if (i == num_params) {
-		printf("Warning: board specific timing not found "
-		"for data rate %lu MT/s!\n", ddr_freq);
-	}
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-
-	/*
-	 * Enable on-die termination.
-	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
-	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
-	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
-	 */
-	popts->rtt_override = 1;
-	popts->rtt_override_value = 3;
-}
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
deleted file mode 100644
index 1e2d604d9d..0000000000
--- a/board/xes/xpedite550x/law.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c
deleted file mode 100644
index 7cb6cd6770..0000000000
--- a/board/xes/xpedite550x/tlb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* W**G* - NOR flashes */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* *I*G* - NAND flash */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 2, BOOKE_PAGESZ_1M, 1),
-
-	/* **M** - Boot page for secondary processors */
-	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
-	/* *I*G* - PCIe */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
deleted file mode 100644
index 9089a0cc72..0000000000
--- a/board/xes/xpedite550x/xpedite550x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
-	int flash_sel;
-
-	/*
-	 * Print boot dev and swap flash flash chip selects if booted from 2nd
-	 * flash.  Swapping chip selects presents user with a common memory
-	 * map regardless of which flash was booted from.
-	 */
-	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
-			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
-	printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
-	if (flash_sel) {
-		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
-		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
-		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
-		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
-	}
-}
-
-int board_early_init_r(void)
-{
-	/* Initialize PCA9557 devices */
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
-	/*
-	 * Remap NOR flash region to caching-inhibited
-	 * so that flash can be erased/programmed properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* Invalidate existing TLB entry for NOR flash */
-	disable_tlb(0);
-	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 0, BOOKE_PAGESZ_256M, 1);
-
-	flash_cs_fixup();
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
-	ft_board_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif