Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup

1 files changed, 0 insertions, 80 deletions

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index fe36cf7eff..e4f86d187a 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -13,27 +13,9 @@
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/ps7_init_gpl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static xilinx_desc fpga;
-
-/* It can be done differently */
-static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
-static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
-static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
-static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
-static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
-#endif
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 static struct udevice *watchdog_dev;
 #endif
@@ -52,46 +34,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-	u32 idcode;
-
-	idcode = zynq_slcr_get_idcode();
-
-	switch (idcode) {
-	case XILINX_ZYNQ_7007S:
-		fpga = fpga007s;
-		break;
-	case XILINX_ZYNQ_7010:
-		fpga = fpga010;
-		break;
-	case XILINX_ZYNQ_7012S:
-		fpga = fpga012s;
-		break;
-	case XILINX_ZYNQ_7014S:
-		fpga = fpga014s;
-		break;
-	case XILINX_ZYNQ_7015:
-		fpga = fpga015;
-		break;
-	case XILINX_ZYNQ_7020:
-		fpga = fpga020;
-		break;
-	case XILINX_ZYNQ_7030:
-		fpga = fpga030;
-		break;
-	case XILINX_ZYNQ_7035:
-		fpga = fpga035;
-		break;
-	case XILINX_ZYNQ_7045:
-		fpga = fpga045;
-		break;
-	case XILINX_ZYNQ_7100:
-		fpga = fpga100;
-		break;
-	}
-#endif
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 		puts("Watchdog: Not found!\n");
@@ -101,12 +43,6 @@ int board_init(void)
 	}
 # endif
 
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
-    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
-	fpga_init();
-	fpga_add(fpga_xilinx, &fpga);
-#endif
-
 	return 0;
 }
 
@@ -136,22 +72,6 @@ int board_late_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	u32 version = zynq_get_silicon_version();
-
-	version <<= 1;
-	if (version > (PCW_SILICON_VERSION_3 << 1))
-		version += 1;
-
-	puts("Board: Xilinx Zynq\n");
-	printf("Silicon: v%d.%d\n", version >> 1, version & 1);
-
-	return 0;
-}
-#endif
-
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \