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authorMichal Simek <michal.simek@xilinx.com>2018-11-29 12:31:02 +0300
committerMichal Simek <michal.simek@xilinx.com>2018-11-29 12:31:02 +0300
commitfdba86972f23cab99710e19a04f36f170d1870e0 (patch)
treef3d40f8eb70814b549f5d445fb1f602d8d9e9744 /board/xilinx
parent6bd13ee94ecf0e3124efdd51758df21db8100083 (diff)
downloadu-boot-fdba86972f23cab99710e19a04f36f170d1870e0.tar.xz
ARM: zynq: Wire SPL configuration for cse nor/nand targets
These symlinks are here only for testing purpose where SPL is used for soc configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/xilinx')
l---------board/xilinx/zynq/zynq-cse-nand1
l---------board/xilinx/zynq/zynq-cse-nor1
2 files changed, 2 insertions, 0 deletions
diff --git a/board/xilinx/zynq/zynq-cse-nand b/board/xilinx/zynq/zynq-cse-nand
new file mode 120000
index 0000000000..9d89a9957e
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-nand
@@ -0,0 +1 @@
+zynq-zc770-xm011 \ No newline at end of file
diff --git a/board/xilinx/zynq/zynq-cse-nor b/board/xilinx/zynq/zynq-cse-nor
new file mode 120000
index 0000000000..bb80693eab
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-nor
@@ -0,0 +1 @@
+zynq-zc770-xm012 \ No newline at end of file