diff options
author | Luka Kovacic <me@lukakovacic.xyz> | 2019-05-07 20:35:55 +0300 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2019-05-09 08:35:04 +0300 |
commit | 22bb913fdf14476b60e1ae86321567116dea5ed7 (patch) | |
tree | cc6db7206c2f2e49b3691b7dc7f6c5084c373608 /board | |
parent | ae436eeb91f61ed687507ebfc8e2afa2574db36a (diff) | |
download | u-boot-22bb913fdf14476b60e1ae86321567116dea5ed7.tar.xz |
arm: mvebu: Add CRS305-1G-4S board
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and
like some of the other similar boards requires bin_hdr.
bin_hdr (DDR3 init stage) is currently retrieved from the stock
bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip
support and writing env to SPI flash.
Signed-off-by: Luka Kovacic <me@lukakovacic.xyz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
-rw-r--r-- | board/mikrotik/crs305-1g-4s/.gitignore | 1 | ||||
-rw-r--r-- | board/mikrotik/crs305-1g-4s/MAINTAINERS | 7 | ||||
-rw-r--r-- | board/mikrotik/crs305-1g-4s/Makefile | 14 | ||||
-rw-r--r-- | board/mikrotik/crs305-1g-4s/README | 23 | ||||
-rw-r--r-- | board/mikrotik/crs305-1g-4s/binary.0 | 11 | ||||
-rw-r--r-- | board/mikrotik/crs305-1g-4s/crs305-1g-4s.c | 75 | ||||
-rw-r--r-- | board/mikrotik/crs305-1g-4s/kwbimage.cfg.in | 12 |
7 files changed, 143 insertions, 0 deletions
diff --git a/board/mikrotik/crs305-1g-4s/.gitignore b/board/mikrotik/crs305-1g-4s/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/mikrotik/crs305-1g-4s/MAINTAINERS b/board/mikrotik/crs305-1g-4s/MAINTAINERS new file mode 100644 index 0000000000..3823489600 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/MAINTAINERS @@ -0,0 +1,7 @@ +CRS305-1G-4S BOARD +M: Luka Kovacic <me@lukakovacic.xyz> +S: Maintained +F: board/mikrotik/crs305-1g-4s/ +F: include/configs/crs305-1g-4s.h +F: configs/crs305-1g-4s_defconfig +F: arch/arm/dts/armada-xp-crs305-1g-4s.dts diff --git a/board/mikrotik/crs305-1g-4s/Makefile b/board/mikrotik/crs305-1g-4s/Makefile new file mode 100644 index 0000000000..895331beb8 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := crs305-1g-4s.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/mikrotik/crs305-1g-4s/README b/board/mikrotik/crs305-1g-4s/README new file mode 100644 index 0000000000..f420aabfbf --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/README @@ -0,0 +1,23 @@ +MikroTik CRS305-1G-4S+IN +======================== + +CRS305-1G-4S+IN is a 4x SFP+ switch with a Gigabit Ethernet port for management. +Specifications: + - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU + - 512 MB DDR3 RAM + - UART @ 115200bps + - 4x SFP+ + - Gigabit Ethernet (AR8033) + - 16 MB SPI flash (Winbond 25Q128JVSM) + +Currently supported hardware: + - UART boot (using kwboot) and console + - SPI boot, environment and load kernel + +Planned: + - Gigabit Ethernet support + +Getting binary.0 +================ +binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash. +Then binary.0 can be replaced with the extracted blob. diff --git a/board/mikrotik/crs305-1g-4s/binary.0 b/board/mikrotik/crs305-1g-4s/binary.0 new file mode 100644 index 0000000000..8dd687286a --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c new file mode 100644 index 0000000000..d1d1f40092 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * These values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2016_T1.0.eng_drop_v6" + */ +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \ + | BIT(6) | BIT(12) | BIT(13) \ + | BIT(16) | BIT(17) | BIT(20) \ + | BIT(29) | BIT(30))) +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \ + | BIT(6) | BIT(12) | BIT(13) \ + | BIT(16) | BIT(17) | BIT(20) \ + | BIT(29) | BIT(30)) +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 +#define DB_DX_AC3_GPP_POL_LOW 0x0 +#define DB_DX_AC3_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00142222, MVEBU_MPP_BASE + 0x00); + writel(0x11122000, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x14444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000001, MVEBU_MPP_BASE + 0x10); + + /* + * MVEBU_GPIO0_BASE is the User LED + * MVEBU_GPIO1_BASE is the Reset Button (currently not used) + */ + + /* Set GPP Out value */ + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + /* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */ + + /* Set GPP Polarity */ + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + /* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */ + + /* Set GPP Out Enable */ + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + /* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */ + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} diff --git a/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in new file mode 100644 index 0000000000..2dbbbd0246 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/mikrotik/crs305-1g-4s/binary.0 0000005b 00000068 |