diff options
author | Yan Hong Wang <yanhong.wang@starfivetech.com> | 2022-09-14 11:44:33 +0300 |
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committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:38 +0300 |
commit | 47e689908a5cca249c036138cc0f4bde014576a2 (patch) | |
tree | 88ba526e988678fbc4fbc44bf5f6c5b2cf4e7279 /board | |
parent | 01bbc04d9d9c9e38e6dcc93b1e7dca57b5862c11 (diff) | |
download | u-boot-47e689908a5cca249c036138cc0f4bde014576a2.tar.xz |
spl: starfive: jh7110: switch pll2 to 1188M
Switch the pll2 clk to 1188M with the comm pll interface on JH7110.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/starfive/evb/spl.c | 176 |
1 files changed, 11 insertions, 165 deletions
diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c index 2a02301b11..b55efa1e81 100644 --- a/board/starfive/evb/spl.c +++ b/board/starfive/evb/spl.c @@ -11,138 +11,13 @@ #include <asm/io.h> #include <asm/arch/gpio.h> #include <asm/arch/jh7110-regs.h> +#include <asm/arch/clk.h> #include <image.h> -#include <linux/bitops.h> #include <log.h> -#include <linux/delay.h> #include <spl.h> #define MODE_SELECT_REG 0x1702002c -struct starfive_pll0_freq { - u32 freq; - u32 prediv; - u32 fbdiv; - u32 postdiv1; - u32 dacpd; /* Both daxpd and dsmpd set 1 while integer multiple mode */ - u32 dsmpd; /* Both daxpd and dsmpd set 0 while fraction multiple mode */ -}; - -enum starfive_cpu_freq { - CPU_FREQ_375 = 0, - CPU_FREQ_500, - CPU_FREQ_625, - CPU_FREQ_750, - CPU_FREQ_875, - CPU_FREQ_1000, - CPU_FREQ_1250, - CPU_FREQ_1375, - CPU_FREQ_1500, - CPU_FREQ_1625, - CPU_FREQ_1750, - CPU_FREQ_1800, - CPU_FREQ_MAX = CPU_FREQ_1800 -}; - -struct starfive_pll0_freq jh7110_pll0_freq[] = { - { - .freq = CPU_FREQ_375, - .prediv = 8, - .fbdiv = 125, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_500, - .prediv = 6, - .fbdiv = 125, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_625, - .prediv = 24, - .fbdiv = 625, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_750, - .prediv = 4, - .fbdiv = 125, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_875, - .prediv = 24, - .fbdiv = 875, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1000, - .prediv = 3, - .fbdiv = 125, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1250, - .prediv = 12, - .fbdiv = 625, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1375, - .prediv = 24, - .fbdiv = 1375, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1500, - .prediv = 2, - .fbdiv = 125, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1625, - .prediv = 24, - .fbdiv = 1625, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1750, - .prediv = 12, - .fbdiv = 875, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, - { - .freq = CPU_FREQ_1800, - .prediv = 3, - .fbdiv = 225, - .postdiv1 = 1, - .dacpd = 1, - .dsmpd = 1 - }, -}; - int spl_board_init_f(void) { int ret; @@ -182,42 +57,15 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR); } -static int spl_cpu_set_rate(enum starfive_cpu_freq rate) -{ - struct starfive_pll0_freq *cpu_freq; - int i; - - if (rate < 0 || rate > CPU_FREQ_MAX) { - debug("invalid input value=%d\n", rate); - return -EINVAL; - } - - for (i = 0; i<CPU_FREQ_MAX; i++) { - if (jh7110_pll0_freq[i].freq == rate) { - cpu_freq = &jh7110_pll0_freq[i]; - break; - } - } - - clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK, - (cpu_freq->dacpd << PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK); - clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK, - (cpu_freq->dsmpd << PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK); - clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK, - (cpu_freq->prediv << PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK); - clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK, - (cpu_freq->fbdiv << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK); - clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK, - ((cpu_freq->postdiv1 >> 1) << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK); - return 0; -} - void board_init_f(ulong dummy) { int ret; /* Adjust cpu frequency, the default is 1.25GHz */ - spl_cpu_set_rate(CPU_FREQ_1250); + starfive_jh7110_pll_set_rate(PLL0, 1250000000); + + /*change pll2 to 1188MHz*/ + starfive_jh7110_pll_set_rate(PLL2, 1188000000); /*DDR control depend clk init*/ clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK, @@ -227,6 +75,11 @@ void board_init_f(ulong dummy) CLK_BUS_ROOT_SW_MASK, BIT(CLK_BUS_ROOT_SW_SHIFT) & CLK_BUS_ROOT_SW_MASK); + /*Set clk_perh_root clk default mux sel to pll2*/ + clrsetbits_le32(SYS_CRG_BASE + CLK_PERH_ROOT_OFFSET, + CLK_PERH_ROOT_MASK, + BIT(CLK_PERH_ROOT_SHIFT) & CLK_PERH_ROOT_MASK); + clrsetbits_le32(SYS_CRG_BASE + CLK_NOC_BUS_STG_AXI_OFFSET, CLK_NOC_BUS_STG_AXI_EN_MASK, BIT(CLK_NOC_BUS_STG_AXI_EN_SHIFT) @@ -236,18 +89,11 @@ void board_init_f(ulong dummy) CLK_AON_APB_FUNC_SW_MASK, BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK); - clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET, - CLK_QSPI_REF_SW_MASK, - (0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK); + /*set GPIO to 1.8v*/ setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf); - /*set sdio0 sdcard clk default div to 4*/ - clrsetbits_le32(SYS_CRG_BASE + CLK_SDIO0_SDCARD_OFFSET, - CLK_SDIO0_SDCARD_MASK, - (4 << CLK_SDIO0_SDCARD_SHIFT) & CLK_SDIO0_SDCARD_MASK); - /* reset emmc */ SYS_IOMUX_DOEN(22, LOW); SYS_IOMUX_DOUT(22, 19); |