Merge https://gitlab.denx.de/u-boot/custodians/u-boot-imx

19 files changed, 511 insertions, 413 deletions

diff --git a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
index b142ee02e6..58a4d253c3 100644
--- a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
+++ b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
@@ -2,5 +2,6 @@ i.MX8QM ROM 7720 a1 BOARD
 M:	Oliver Graute <oliver.graute@kococonnector.com>
 S:	Maintained
 F:	board/advantech/imx8qm_rom7720_a1/
+F:	arch/arm/dts/imx8qm-rom7720-a1.dts
 F:	include/configs/imx8qm_rom7720.h
 F:	configs/imx8qm_rom7720_a1_4G_defconfig
diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README
deleted file mode 100644
index 585fde440d..0000000000
--- a/board/advantech/imx8qm_rom7720_a1/README
+++ /dev/null
@@ -1,61 +0,0 @@
-U-Boot for the NXP i.MX8QM ROM 7720a1 board
-
-Quick Start
-===========
-
-- Build the ARM Trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Get imx-mkimage
-- Build U-Boot
-- Build imx-mkimage
-- Flash the binary into the SD card
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-
-$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
-$ make PLAT=imx8qm bl31
-
-Get scfw_tcm.bin and ahab-container.img
-==============================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
-$ chmod +x imx-sc-firmware-1.1.bin
-$ ./imx-sc-firmware-1.1.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Or use this to avoid running random scripts from the internet,
-but note that you must agree to the license the script displays:
-
-$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
-$ tar -xf imx-sc-firmware-1.1.tar.bz2
-$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
-
-$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
-$ tar -xf firmware-imx-8.0.tar.bz2
-$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
-
-Build U-Boot
-============
-
-$ export ATF_LOAD_ADDR=0x80000000
-$ export BL33_LOAD_ADDR=0x80020000
-$ make imx8qm_rom7720_a1_4G_defconfig
-$ make u-boot.bin
-$ make flash.bin
-
-Flash the binary into the SD card
-=================================
-
-Burn the flash.bin binary to SD card offset 32KB:
-
-$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
-
-Boot
-====
-Set Boot switch SW2: 1100.
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index 2ad3dbd56c..cc603c1bc2 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -1,28 +1,4 @@
-if TARGET_ARISTAINETOS2
-
-source "board/aristainetos/common/Kconfig"
-
-config SYS_BOARD
-	default "aristainetos"
-
-config SYS_BOARD_VERSION
-	default 2
-
-endif
-
-if TARGET_ARISTAINETOS2B
-
-source "board/aristainetos/common/Kconfig"
-
-config SYS_BOARD
-	default "aristainetos"
-
-config SYS_BOARD_VERSION
-	default 3
-
-endif
-
-if TARGET_ARISTAINETOS2BCSL
+if TARGET_ARISTAINETOS2C
 
 source "board/aristainetos/common/Kconfig"
 
@@ -30,11 +6,11 @@ config SYS_BOARD
 	default "aristainetos"
 
 config SYS_BOARD_VERSION
-	default 4
+	default 5
 
 endif
 
-if TARGET_ARISTAINETOS2C
+if TARGET_ARISTAINETOS2CCSLB
 
 source "board/aristainetos/common/Kconfig"
 
@@ -42,6 +18,6 @@ config SYS_BOARD
 	default "aristainetos"
 
 config SYS_BOARD_VERSION
-	default 5
+	default 6
 
 endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index b4ca7abb9c..c81bef9cb7 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -3,34 +3,16 @@ M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/aristainetos/
 F:	include/configs/aristainetos2.h
-F:	configs/aristainetos2_defconfig
-F:	configs/aristainetos2b_defconfig
-F:	configs/aristainetos2bcsl_defconfig
 F:	configs/aristainetos2c_defconfig
-F:	arch/arm/dts/imx6qdl-aristainetos2.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_7.dts
-F:	arch/arm/dts/imx6dl-aristainetos2_7.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2_4.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_7.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
-F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
-F:	arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
-F:	arch/arm/dts/imx6dl-aristainetos2c_4.dts
-F:	arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+F:	configs/aristainetos2ccslb_defconfig
 F:	arch/arm/dts/imx6dl-aristainetos2c_7.dts
 F:	arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2c.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 14931120f6..07d2e3ec7b 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -27,6 +27,7 @@
 #include <bmp_logo.h>
 #include <dm/root.h>
 #include <env.h>
+#include <env_internal.h>
 #include <i2c_eeprom.h>
 #include <i2c.h>
 #include <micrel.h>
@@ -194,87 +195,6 @@ static void enable_lvds(struct display_info_t const *dev)
 	writel(reg, &iomux->gpr[3]);
 }
 
-static void enable_spi_display(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	int reg;
-	s32 timeout = 100000;
-
-#if defined(CONFIG_VIDEO_BMP_LOGO)
-	rotate_logo(3);  /* portrait display in landscape mode */
-#endif
-
-	reg = readl(&ccm->cs2cdr);
-
-	/* select pll 5 clock */
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	writel(reg, &ccm->cs2cdr);
-
-	/* set PLL5 to 197994996Hz */
-	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
-	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
-	writel(reg, &ccm->analog_pll_video);
-
-	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
-	       &ccm->analog_pll_video_num);
-	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
-	       &ccm->analog_pll_video_denom);
-
-	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
-	writel(reg, &ccm->analog_pll_video);
-
-	while (timeout--)
-		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
-			break;
-	if (timeout < 0)
-		printf("Warning: video pll lock timeout!\n");
-
-	reg = readl(&ccm->analog_pll_video);
-	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
-	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
-	writel(reg, &ccm->analog_pll_video);
-
-	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
-	reg = readl(&ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &ccm->cs2cdr);
-
-	reg = readl(&ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &ccm->cscmr2);
-
-	reg = readl(&ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
-	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
-	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
-	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
-	writel(reg, &ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
-	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
-	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-}
-
 static void setup_display(void)
 {
 	enable_ipu_clock();
@@ -331,25 +251,36 @@ static void setup_board_gpio(void)
 	setup_one_led("led_blue", LEDST_OFF);
 }
 
-#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
-		" rescueReason=%d "
-
 static void aristainetos_run_rescue_command(int reason)
 {
-	char rescue_reason_command[80];
+	char rescue_reason_command[20];
 
-	sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
+	sprintf(rescue_reason_command, "setenv rreason %d", reason);
 	run_command(rescue_reason_command, 0);
 }
 
-static int aristainetos_eeprom(void)
+static int aristainetos_bootmode_settings(void)
 {
+	struct gpio_desc *desc;
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int sbmr1 = readl(&psrc->sbmr1);
+	char *my_bootdelay;
+	char bootmode = 0;
+	int ret;
 	struct udevice *dev;
 	int off;
-	int ret;
 	u8 data[0x10];
 	u8 rescue_reason;
 
+	/* jumper controlled reset of the environment */
+	ret = gpio_hog_lookup_name("env_reset", &desc);
+	if (!ret) {
+		if (dm_gpio_get_value(desc)) {
+			printf("\nReset u-boot environment (jumper)\n");
+			run_command("run default_env; saveenv; saveenv", 0);
+		}
+	}
+
 	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 	if (off < 0) {
 		printf("%s: No eeprom0 path offset\n", __func__);
@@ -366,37 +297,26 @@ static int aristainetos_eeprom(void)
 	if (ret)
 		return ret;
 
-	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
+	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
 	if (ret) {
 		printf("%s: Could not read EEPROM\n", __func__);
 		return ret;
 	}
 
-	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
-		rescue_reason = *(uint8_t *)&data[9];
-		memset(&data[3], 0xff, 7);
-		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
-		printf("\nBooting into Rescue System (EEPROM)\n");
-		aristainetos_run_rescue_command(rescue_reason);
-		run_command("run rescue_load_fit rescueboot", 0);
-	} else if (strncmp((char *)data, "DeF", 3) == 0) {
+	/* software controlled reset of the environment (EEPROM magic) */
+	if (strncmp((char *)data, "DeF", 3) == 0) {
 		memset(data, 0xff, 3);
 		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
-		printf("\nClear u-boot environment (set back to defaults)\n");
+		printf("\nReset u-boot environment (EEPROM)\n");
 		run_command("run default_env; saveenv; saveenv", 0);
 	}
 
-	return 0;
-};
-
-static void aristainetos_bootmode_settings(void)
-{
-	struct gpio_desc *desc;
-	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-	unsigned int sbmr1 = readl(&psrc->sbmr1);
-	char *my_bootdelay;
-	char bootmode = 0;
-	int ret;
+	if (sbmr1 & 0x40) {
+		env_set("bootmode", "1");
+		printf("SD bootmode jumper set!\n");
+	} else {
+		env_set("bootmode", "0");
+	}
 
 	/*
 	 * Check the boot-source. If booting from NOR Flash,
@@ -420,28 +340,27 @@ static void aristainetos_bootmode_settings(void)
 			env_set("bootdelay", "-2");
 	}
 
-	if (sbmr1 & 0x40) {
-		env_set("bootmode", "1");
-		printf("SD bootmode jumper set!\n");
-	} else {
-		env_set("bootmode", "0");
-	}
-
-	/* read out some jumper values*/
-	ret = gpio_hog_lookup_name("env_reset", &desc);
-	if (!ret) {
-		if (dm_gpio_get_value(desc)) {
-			printf("\nClear env (set back to defaults)\n");
-			run_command("run default_env; saveenv; saveenv", 0);
-		}
-	}
+	/* jumper controlled boot of the rescue system */
 	ret = gpio_hog_lookup_name("boot_rescue", &desc);
 	if (!ret) {
 		if (dm_gpio_get_value(desc)) {
+			printf("\nBooting into Rescue System (jumper)\n");
 			aristainetos_run_rescue_command(16);
 			run_command("run rescue_xload_boot", 0);
 		}
 	}
+
+	/* software controlled boot of the rescue system (EEPROM magic) */
+	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
+		rescue_reason = *(uint8_t *)&data[9];
+		memset(&data[3], 0xff, 7);
+		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
+		printf("\nBooting into Rescue System (EEPROM)\n");
+		aristainetos_run_rescue_command(rescue_reason);
+		run_command("run rescue_xload_boot", 0);
+	}
+
+	return 0;
 }
 
 #if defined(CONFIG_DM_PMIC_DA9063)
@@ -497,15 +416,15 @@ static int setup_pmic_voltages(void)
 int board_late_init(void)
 {
 	int x, y;
+	int ret;
 
 	led_default_state();
 	splash_get_pos(&x, &y);
 	bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 
-	aristainetos_bootmode_settings();
-
-	/* eeprom work */
-	aristainetos_eeprom();
+	ret = aristainetos_bootmode_settings();
+	if (ret)
+		return ret;
 
 	/* set board_type */
 	if (gd->board_type == BOARD_TYPE_4)
@@ -549,97 +468,9 @@ struct display_info_t const displays[] = {
 			.vmode          = FB_VMODE_NONINTERLACED
 		}
 	}
-#if ((CONFIG_SYS_BOARD_VERSION == 2) || \
-	(CONFIG_SYS_BOARD_VERSION == 3) || \
-	(CONFIG_SYS_BOARD_VERSION == 4) || \
-	(CONFIG_SYS_BOARD_VERSION == 5))
-	, {
-		.bus	= -1,
-		.addr	= 0,
-		.pixfmt	= IPU_PIX_FMT_RGB24,
-		.detect	= NULL,
-		.enable	= enable_spi_display,
-		.mode	= {
-			.name           = "lg4573",
-			.refresh        = 57,
-			.xres           = 480,
-			.yres           = 800,
-			.pixclock       = 37037,
-			.left_margin    = 59,
-			.right_margin   = 10,
-			.upper_margin   = 15,
-			.lower_margin   = 15,
-			.hsync_len      = 10,
-			.vsync_len      = 15,
-			.sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
-					  FB_SYNC_VERT_HIGH_ACT,
-			.vmode          = FB_VMODE_NONINTERLACED
-		}
-	}
-#endif
 };
 size_t display_count = ARRAY_SIZE(displays);
 
-#if defined(CONFIG_MTD_RAW_NAND)
-iomux_v3_cfg_t nfc_pads[] = {
-	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__NAND_CE0_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D0__NAND_DATA00		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D1__NAND_DATA01		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D2__NAND_DATA02		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D3__NAND_DATA03		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D4__NAND_DATA04		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D5__NAND_DATA05		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D6__NAND_DATA06		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D7__NAND_DATA07		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nfc_pads,
-					 ARRAY_SIZE(nfc_pads));
-
-	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
-	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-	/* config gpmi and bch clock to 100 MHz */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-	/* enable ENFC_CLK_ROOT clock */
-	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-	/* enable gpmi and bch clock gating */
-	setbits_le32(&mxc_ccm->CCGR4,
-		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#else
-static void setup_gpmi_nand(void)
-{
-}
-#endif
-
 int board_init(void)
 {
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -648,7 +479,6 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 	setup_board_gpio();
-	setup_gpmi_nand();
 	setup_display();
 
 	/* GPIO_1 for USB_OTG_ID */
@@ -698,3 +528,22 @@ int embedded_dtb_select(void)
 	return 0;
 }
 #endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_SPI_FLASH;
+
+	switch (prio) {
+	case 0:
+		return ENVL_NOWHERE;
+
+	case 1:
+		return ENVL_SPI_FLASH;
+
+	default:
+		return ENVL_UNKNOWN;
+	}
+
+	return ENVL_UNKNOWN;
+}
diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig
index e26de5144d..328243c2f9 100644
--- a/board/aristainetos/common/Kconfig
+++ b/board/aristainetos/common/Kconfig
@@ -2,10 +2,8 @@ config SYS_BOARD_VERSION
 	int "select version of aristainetos board"
 	help
 	  version of aristainetos board version
-	  2 version 2
-	  3 version 2b
-	  4 version 2bcsl
-	  5 version 2c
+	  5 version 2c and 2d
+	  6 version 2c-cslb
 
 config SYS_I2C_MXC_I2C1
 	default y
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 8a38ac5d4e..4754647fb4 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -43,28 +43,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int confidx;  /* Default to generic. */
+#define VPD_PRODUCT_B850 1
+#define VPD_PRODUCT_B650 2
+#define VPD_PRODUCT_B450 3
+
+static int productid;  /* Default to generic. */
 static struct vpd_cache vpd;
 
 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
 	PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
-	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -127,7 +116,7 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 
 static int is_b850v3(void)
 {
-	return confidx == 3;
+	return productid == VPD_PRODUCT_B850;
 }
 
 static int detect_lcd(struct display_info_t const *dev)
@@ -314,9 +303,6 @@ int overwrite_console(void)
 #define VPD_TYPE_INVALID 0x00
 #define VPD_BLOCK_NETWORK 0x20
 #define VPD_BLOCK_HWID 0x44
-#define VPD_PRODUCT_B850 1
-#define VPD_PRODUCT_B650 2
-#define VPD_PRODUCT_B450 3
 #define VPD_HAS_MAC1 0x1
 #define VPD_HAS_MAC2 0x2
 #define VPD_MAC_ADDRESS_LENGTH 6
@@ -398,6 +384,7 @@ static iomux_v3_cfg_t const misc_pads[] = {
 	MX6_PAD_GPIO_9__WDOG1_B         | MUX_PAD_CTRL(NC_PAD_CTRL),
 };
 #define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
+#define PWGIN_IN	IMX_GPIO_NR(4, 14)
 #define WIFI_EN	IMX_GPIO_NR(6, 14)
 
 int board_early_init_f(void)
@@ -412,28 +399,13 @@ int board_early_init_f(void)
 	return 0;
 }
 
-static void set_confidx(const struct vpd_cache* vpd)
-{
-	switch (vpd->product_id) {
-	case VPD_PRODUCT_B450:
-		confidx = 1;
-		break;
-	case VPD_PRODUCT_B650:
-		confidx = 2;
-		break;
-	case VPD_PRODUCT_B850:
-		confidx = 3;
-		break;
-	}
-}
-
 int board_init(void)
 {
 	if (!read_i2c_vpd(&vpd, vpd_callback)) {
 		int ret, rescan;
 
 		vpd.is_read = true;
-		set_confidx(&vpd);
+		productid = vpd.product_id;
 
 		ret = fdtdec_resetup(&rescan);
 		if (!ret && rescan) {
@@ -445,6 +417,9 @@ int board_init(void)
 	gpio_request(SUS_S3_OUT, "sus_s3_out");
 	gpio_direction_output(SUS_S3_OUT, 1);
 
+	gpio_request(PWGIN_IN, "pwgin_in");
+	gpio_direction_input(PWGIN_IN);
+
 	gpio_request(WIFI_EN, "wifi_en");
 	gpio_direction_output(WIFI_EN, 1);
 
@@ -494,6 +469,17 @@ void pmic_init(void)
 	}
 }
 
+static void detect_boot_cause(void)
+{
+	const char *cause = "POR";
+
+	if (is_b850v3())
+		if (!gpio_get_value(PWGIN_IN))
+			cause = "PM_WDOG";
+
+	env_set("bootcause", cause);
+}
+
 int board_late_init(void)
 {
 	process_vpd(&vpd);
@@ -507,6 +493,8 @@ int board_late_init(void)
 	else
 		env_set("videoargs", "video=LVDS-1:1024x768@65");
 
+	detect_boot_cause();
+
 	/* board specific pmic init */
 	pmic_init();
 
diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c
index 421fee5922..c28d2c03cf 100644
--- a/board/ge/common/vpd_reader.c
+++ b/board/ge/common/vpd_reader.c
@@ -209,7 +209,7 @@ int read_i2c_vpd(struct vpd_cache *cache,
 	u8 *data;
 	int size;
 
-	ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev);
+	ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev);
 	if (ret)
 		return ret;
 
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 9263b0f51f..2ed66261d2 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -37,6 +37,29 @@ static void setup_iomux_uart(void)
 	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_quadplus = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* QP has one A72 core disabled */
+		is_quadplus = ((val >> 4) & 0x3) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	if (is_quadplus)
+		/* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
+		*phys_sdram_2_size = 0x0UL;
+	else
+		*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
 int board_early_init_f(void)
 {
 	sc_pm_clock_rate_t rate = SC_80MHZ;
diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig
new file mode 100644
index 0000000000..ee61e09736
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_IMX8X
+
+config SYS_BOARD
+	default "apalis-imx8x"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-imx8x"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS
new file mode 100644
index 0000000000..fbf9379931
--- /dev/null
+++ b/board/toradex/apalis-imx8x/MAINTAINERS
@@ -0,0 +1,10 @@
+Apalis iMX8X
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	arch/arm/dts/fsl-imx8x-apalis.dts
+F:	arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi
+F:	board/toradex/apalis-imx8x/
+F:	configs/apalis-imx8x_defconfig
+F:	doc/board/toradex/apalis-imx8x.rst
+F:	include/configs/apalis-imx8x.h
diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile
new file mode 100644
index 0000000000..9d6e85b742
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Toradex
+#
+
+obj-y += apalis-imx8x.o
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
new file mode 100644
index 0000000000..58c62d0a65
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c
new file mode 100644
index 0000000000..739d2e5155
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart1_pads[] = {
+	SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_dualx = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* DX has two A35 cores disabled */
+		is_dualx = (val & 0xf) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	if (is_dualx)
+		/* Our DX based SKUs only have 1 GB RAM */
+		*phys_sdram_1_size = SZ_1G;
+	else
+		*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate;
+	sc_err_t err = 0;
+
+	/*
+	 * This works around that having only UART3 up the baudrate is 1.2M
+	 * instead of 115.2k. Set UART0 clock root to 80 MHz
+	 */
+	rate = 80000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	/* Set UART3 clock root to 80 MHz and enable it */
+	rate = SC_80MHZ;
+	err = sc_pm_setup_uart(SC_R_UART_1, rate);
+	if (err != SC_ERR_NONE)
+		return 0;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+	/* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis iMX8X\n");
+
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+	env_set("board_name", "Apalis iMX8X");
+#endif
+
+	return 0;
+}
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index f981c11a37..da081e30be 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -39,6 +39,29 @@ static void setup_iomux_uart(void)
 	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 }
 
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+			  u64 *phys_sdram_1_size,
+			  u64 *phys_sdram_2_start,
+			  u64 *phys_sdram_2_size)
+{
+	u32 is_dualx = 0, val = 0;
+	sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+	if (scierr == SC_ERR_NONE) {
+		/* DX has two A35 cores disabled */
+		is_dualx = (val & 0xf) != 0x0;
+	}
+
+	*phys_sdram_1_start = PHYS_SDRAM_1;
+	if (is_dualx)
+		/* Our DX based SKUs only have 1 GB RAM */
+		*phys_sdram_1_size = SZ_1G;
+	else
+		*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+	*phys_sdram_2_start = PHYS_SDRAM_2;
+	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
 int board_early_init_f(void)
 {
 	sc_pm_clock_rate_t rate;
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index bf27b2fa66..adab0a0802 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -16,7 +16,8 @@
 	defined(CONFIG_TARGET_COLIBRI_IMX6) || \
 	defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
 	defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
-	defined(CONFIG_TARGET_VERDIN_IMX8MN)
+	defined(CONFIG_TARGET_VERDIN_IMX8MN) || \
+	defined(CONFIG_TARGET_VERDIN_IMX8MP)
 #include <asm/arch/sys_proto.h>
 #else
 #define is_cpu_type(cpu) (0)
@@ -137,8 +138,12 @@ const char * const toradex_modules[] = {
 	[53] = "Apalis iMX8 QuadXPlus 2GB ECC IT",
 	[54] = "Apalis iMX8 DualXPlus 1GB",
 	[55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT",
-	[56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */
+	[56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */
 	[57] = "Verdin iMX8M Mini DualLite 1GB",
+	[58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT",
+	[59] = "Verdin iMX8M Mini Quad 2GB IT",
+	[60] = "Verdin iMX8M Mini DualLite 1GB WB IT",
+	[61] = "Verdin iMX8M Plus Quad 2GB",
 };
 
 const char * const toradex_carrier_boards[] = {
@@ -361,21 +366,15 @@ static int get_cfgblock_interactive(void)
 
 	if (cpu_is_pxa27x())
 		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
-#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) || !defined(CONFIG_TARGET_VERDIN_IMX8MN)
-	else
-		sprintf(message, "Is the module an IT version? [y/N] ");
-
-	len = cli_readline(message);
-	it = console_buffer[0];
-#else
 	else
 		it = 'y';
-#endif
 
 #if defined(CONFIG_TARGET_APALIS_IMX8) || \
 		defined(CONFIG_TARGET_APALIS_IMX8X) || \
 		defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
-		defined(CONFIG_TARGET_COLIBRI_IMX8X)
+		defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
+		defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
+		defined(CONFIG_TARGET_VERDIN_IMX8MP)
 	sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
 	len = cli_readline(message);
 	wb = console_buffer[0];
@@ -424,12 +423,6 @@ static int get_cfgblock_interactive(void)
 		tdx_hw_tag.prodid = COLIBRI_IMX7D;
 	else if (!strcmp("imx7s", soc))
 		tdx_hw_tag.prodid = COLIBRI_IMX7S;
-	else if (is_cpu_type(MXC_CPU_IMX8MM))
-		tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
-	else if (is_cpu_type(MXC_CPU_IMX8MMDL))
-		tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
-	else if (is_cpu_type(MXC_CPU_IMX8MN))
-		tdx_hw_tag.prodid = VERDIN_IMX8MNSL;
 	else if (is_cpu_type(MXC_CPU_IMX8QM)) {
 		if (it == 'y' || it == 'Y') {
 			if (wb == 'y' || wb == 'Y')
@@ -465,6 +458,23 @@ static int get_cfgblock_interactive(void)
 				tdx_hw_tag.prodid = COLIBRI_IMX8DX;
 		}
 #endif
+	} else if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
+	} else if (is_cpu_type(MXC_CPU_IMX8MM)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
+	} else if (is_cpu_type(MXC_CPU_IMX8MN)) {
+		tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
+	} else if (is_cpu_type(MXC_CPU_IMX8MP)) {
+		if (wb == 'y' || wb == 'Y')
+			tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
+		else
+			tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
 	} else if (!strcmp("tegra20", soc)) {
 		if (it == 'y' || it == 'Y')
 			if (gd->ram_size == 0x10000000)
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 8f91d9aec6..9debd5f046 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -75,9 +75,13 @@ enum {
 	COLIBRI_IMX8DX,
 	APALIS_IMX8QXP,
 	APALIS_IMX8DXP,
-	VERDIN_IMX8MMQ_WIFI_BT_IT,
-	VERDIN_IMX8MNSL,
+	VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */
+	VERDIN_IMX8MNQ_WIFI_BT,
 	VERDIN_IMX8MMDL,
+	VERDIN_IMX8MPQ_WIFI_BT_IT,
+	VERDIN_IMX8MMQ_IT,
+	VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */
+	VERDIN_IMX8MPQ,
 };
 
 enum {
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index cc78c5666b..72e2e09e25 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -21,12 +21,16 @@
 #include <dm/uclass.h>
 #include <dm/uclass-internal.h>
 #include <hang.h>
+#include <i2c.h>
 #include <power/bd71837.h>
+#include <power/pca9450.h>
 #include <power/pmic.h>
 #include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define I2C_PMIC_BUS_ID        1
+
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
@@ -101,33 +105,29 @@ int power_init_board(void)
 	struct udevice *dev;
 	int ret;
 
-	ret = pmic_get("pmic@4b", &dev);
-	if (ret == -ENODEV) {
-		puts("No pmic\n");
-		return 0;
-	}
-	if (ret != 0)
-		return ret;
+	if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
+		ret = pmic_get("pmic", &dev);
+		if (ret == -ENODEV) {
+			puts("No pmic found\n");
+			return ret;
+		}
 
-	/* decrease RESET key long push time from the default 10s to 10ms */
-	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+		if (ret != 0)
+			return ret;
 
-	/* unlock the PMIC regs */
-	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+		/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+		pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
 
-	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
-	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+		/* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
 
-	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
-	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+		/* set WDOG_B_CFG to cold reset */
+		pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
 
-#ifndef CONFIG_IMX8M_LPDDR4
-	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
-	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
-#endif
+		pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
 
-	/* lock the PMIC regs */
-	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+		return 0;
+	}
 
 	return 0;
 }
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 66950ed218..7cfae8767c 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -8,12 +8,22 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <i2c.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <micrel.h>
 
+#include "../common/tdx-cfg-block.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#define I2C_PMIC	0
+
+enum pcb_rev_t {
+	PCB_VERSION_1_0,
+	PCB_VERSION_1_1
+};
+
 #if IS_ENABLED(CONFIG_FEC_MXC)
 static int setup_fec(void)
 {
@@ -104,8 +114,79 @@ int board_mmc_get_env_dev(int devno)
 	return devno;
 }
 
+static enum pcb_rev_t get_pcb_revision(void)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	u8 is_bd71837 = 0;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, &bus);
+	if (!ret)
+		ret = dm_i2c_probe(bus, 0x4b, 0, &i2c_dev);
+	if (!ret)
+		ret = dm_i2c_read(i2c_dev, 0x0, &is_bd71837, 1);
+
+	/* BD71837_REV, High Nibble is major version, fix 1010 */
+	is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0);
+	return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1;
+}
+
+static void select_dt_from_module_version(void)
+{
+	char variant[32];
+	char *env_variant = env_get("variant");
+	int is_wifi = 0;
+
+	if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+		/*
+		 * If we have a valid config block and it says we are a
+		 * module with Wi-Fi/Bluetooth make sure we use the -wifi
+		 * device tree.
+		 */
+		is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT);
+	}
+
+	switch (get_pcb_revision()) {
+	case PCB_VERSION_1_0:
+		printf("Detected a V1.0 module\n");
+		if (is_wifi)
+			strncpy(&variant[0], "wifi", sizeof(variant));
+		else
+			strncpy(&variant[0], "nonwifi", sizeof(variant));
+		break;
+	default:
+		if (is_wifi)
+			strncpy(&variant[0], "wifi-v1.1", sizeof(variant));
+		else
+			strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant));
+		break;
+	}
+
+	if (strcmp(variant, env_variant)) {
+		printf("Setting variant to %s\n", variant);
+		env_set("variant", variant);
+
+		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+			env_save();
+	}
+}
+
 int board_late_init(void)
 {
+	select_dt_from_module_version();
+
+	return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
 	return 0;
 }