diff options
author | Holger Brunck <holger.brunck@ch.abb.com> | 2020-02-19 21:55:14 +0300 |
---|---|---|
committer | Marek Vasut <marex@denx.de> | 2020-03-04 00:11:36 +0300 |
commit | 468ba8d00b5af7828302e297736ae23d4873cfb0 (patch) | |
tree | 1a60a77e307bbd56fb4733807d3c8a2586f80508 /board | |
parent | 85f748ad953e92e62831bff24bfd2260ef23325c (diff) | |
download | u-boot-468ba8d00b5af7828302e297736ae23d4873cfb0.tar.xz |
ARM: socfpga: Add initial support for the ABB SECU board
Add initial support for the ABB SECU board, which is an ArriaV-based
SoCFPGA system with ethernet and booting from Denali NAND.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/keymile/Kconfig | 11 | ||||
-rw-r--r-- | board/keymile/common/ivm.c | 19 | ||||
-rw-r--r-- | board/keymile/secu1/MAINTAINERS | 5 | ||||
-rw-r--r-- | board/keymile/secu1/Makefile | 7 | ||||
-rw-r--r-- | board/keymile/secu1/qts/iocsr_config.h | 694 | ||||
-rw-r--r-- | board/keymile/secu1/qts/pinmux_config.h | 218 | ||||
-rw-r--r-- | board/keymile/secu1/qts/pll_config.h | 83 | ||||
-rw-r--r-- | board/keymile/secu1/qts/sdram_config.h | 327 | ||||
-rw-r--r-- | board/keymile/secu1/socfpga.c | 67 |
9 files changed, 1427 insertions, 4 deletions
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 634dbbe097..7f4cad86aa 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -14,6 +14,7 @@ menu "KM Board Setup" config KM_PNVRAM hex "Pseudo RAM" default 0x80000 + depends on !ARCH_SOCFPGA help Start address of the pseudo non-volatile RAM for application. @@ -21,6 +22,7 @@ config KM_PHRAM hex "Physical RAM" default 0x17F000 if ARM default 0x100000 if PPC + depends on !ARCH_SOCFPGA help Start address of the physical RAM, which is the mounted /var folder. @@ -29,6 +31,7 @@ config KM_RESERVED_PRAM default 0x801000 if KIRKWOOD default 0x0 if MPC83xx default 0x1000 if MPC85xx + depends on !ARCH_SOCFPGA help Reserved physical RAM area at the end of memory for special purposes. @@ -37,6 +40,7 @@ config KM_CRAMFS_ADDR default 0x2400000 if KIRKWOOD default 0xC00000 if MPC83xx default 0x2000000 if MPC85xx + depends on !ARCH_SOCFPGA help Start address of the CRAMFS containing the Linux kernel. @@ -44,13 +48,13 @@ config KM_KERNEL_ADDR hex "Kernel Load Address" default 0x2000000 if KIRKWOOD default 0x400000 if MPC83xx - default 0x1000000 if MPC85xx + default 0x1000000 if MPC85xx || ARCH_SOCFPGA help Address where to load Linux kernel in RAM. config KM_FDT_ADDR hex "FDT Load Address" - default 0x23E0000 if KIRKWOOD + default 0x23E0000 if KIRKWOOD || ARCH_SOCFPGA default 0xB80000 if MPC83xx default 0x1F80000 if MPC85xx help @@ -71,7 +75,7 @@ config KM_DEF_NETDEV config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" default y if KIRKWOOD || MPC83xx - default n if MPC85xx + default n if MPC85xx || ARCH_SOCFPGA help Use the Ethernet initialization implemented in common code, which detects if a Piggy board is present. @@ -91,6 +95,7 @@ config KM_MVEXTSW_ADDR config KM_IVM_BUS int "IVM I2C Bus" + default 0 if ARCH_SOCFPGA default 1 if KIRKWOOD || MPC85xx default 2 if MPC83xx help diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index fee7f03c8c..60b89fe348 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -328,7 +328,24 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset) int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *eedev = NULL; + + ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS, + CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev); + if (ret) { + printf("failed to get device for EEPROM at address 0x%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return 1; + } + ret = dm_i2c_read(eedev, 0, buf, len); + if (ret != 0) { + printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n", + CONFIG_SYS_I2C_EEPROM_ADDR, 0); + return 1; + } +#else i2c_set_bus_num(CONFIG_KM_IVM_BUS); /* add deblocking here */ i2c_make_abort(); @@ -338,6 +355,6 @@ int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset) printf("Error reading EEprom\n"); return -2; } - +#endif return ivm_populate_env(buf, len, mac_address_offset); } diff --git a/board/keymile/secu1/MAINTAINERS b/board/keymile/secu1/MAINTAINERS new file mode 100644 index 0000000000..5dc4aa6a68 --- /dev/null +++ b/board/keymile/secu1/MAINTAINERS @@ -0,0 +1,5 @@ +ABB SECU1 BOARD +M: Holger Brunck <holger.brunck@ch.abb.com> +S: Maintained +F: include/configs/socfpga_arria5_secu1.h +F: configs/socfpga_secu1_defconfig diff --git a/board/keymile/secu1/Makefile b/board/keymile/secu1/Makefile new file mode 100644 index 0000000000..4704d59e48 --- /dev/null +++ b/board/keymile/secu1/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2020 ABB +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o ../common/ivm.o diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h new file mode 100644 index 0000000000..7640c56db1 --- /dev/null +++ b/board/keymile/secu1/qts/iocsr_config.h @@ -0,0 +1,694 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x00001000, + 0x00000000, + 0x0300C000, + 0x0000000C, + 0x00000000, + 0x00000000, + 0x00000800, + 0x01806018, + 0x00000000, + 0x01800000, + 0x00001806, + 0x00001806, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x00020000, + 0x08000000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00006018, + 0x01806000, + 0x00000006, + 0x00000008, + 0x00601806, + 0x00000400, + 0x0000300C, + 0x00C03000, + 0x00C00000, + 0x00000003, + 0x00000C03, + 0x00000200, + 0x00000000, + 0x00601800, + 0x80600000, + 0x80000001, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x00018060, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x00001000, + 0x0300C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, + 0x01806018, + 0x01806000, + 0x00000006, + 0x00000000, + 0x00601806, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, + 0x00601806, + 0x80601800, + 0x80600001, + 0x80000601, + 0x00180601, + 0x00000100, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x2CC20D80, + 0x082000FF, + 0x08028001, + 0x00100000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x00000000, + 0xC0000010, + 0x00C00512, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xA2580000, + 0x60001800, + 0x00600289, + 0x800A2580, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x512C0000, + 0xB0000C00, + 0x00300144, + 0xC00512C0, + 0x144B0000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xA0680514, + 0xC3034028, + 0x06181A00, + 0x805140D0, + 0x34069A06, + 0x01A034D0, + 0x240D0000, + 0x28A06809, + 0x00000340, + 0xD000001A, + 0x06809240, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x80000000, + 0x01800A25, + 0x00289600, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x44B00000, + 0xC0003001, + 0x00C00512, + 0x00000FF0, + 0x512C0000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x581D8000, + 0x60001800, + 0x00600289, + 0x800A2580, + 0x16076001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x512C0000, + 0xB0000C00, + 0x00300144, + 0xC00512C0, + 0x144B0000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xA0680514, + 0x4D034028, + 0x1A681A03, + 0x805140D0, + 0x34069A06, + 0x01A00020, + 0x240D0001, + 0x49206809, + 0x034D0340, + 0xD01A681A, + 0x06805140, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x80000000, + 0x01800A25, + 0x00289600, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x44B0090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x1C864000, + 0x45147A07, + 0xA228A3DA, + 0xF491451E, + 0x0358D348, + 0x821A0000, + 0x0000D000, + 0x028A0680, + 0xDA79E47A, + 0x1EA228A3, + 0xC8F49965, + 0x000344B2, + 0x00080000, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x60120800, + 0x00600289, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xC228A3DC, + 0xF491451E, + 0x0344B2C8, + 0x821A034D, + 0x0000D000, + 0x00000680, + 0xD469A47A, + 0x1E83CF23, + 0xC8F71E79, + 0x000344B2, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820008, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010000, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0x92AAA3D2, + 0xF595551E, + 0x034CF3C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDA79E47A, + 0x1EA32CA3, + 0xC8F69965, + 0x000354F3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820008, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020000, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00002000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xC3CF23DC, + 0xF711451E, + 0x0358D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD459647A, + 0x1E83CF23, + 0x48F51E79, + 0x000348D3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000020, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820008, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00008000, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x00000000, + 0x00000010, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00141419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/pinmux_config.h b/board/keymile/secu1/qts/pinmux_config.h new file mode 100644 index 0000000000..a9406060ed --- /dev/null +++ b/board/keymile/secu1/qts/pinmux_config.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 3, /* EMACIO0 */ + 3, /* EMACIO1 */ + 3, /* EMACIO2 */ + 3, /* EMACIO3 */ + 3, /* EMACIO4 */ + 3, /* EMACIO5 */ + 3, /* EMACIO6 */ + 3, /* EMACIO7 */ + 3, /* EMACIO8 */ + 3, /* EMACIO9 */ + 3, /* EMACIO10 */ + 3, /* EMACIO11 */ + 3, /* EMACIO12 */ + 3, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 0, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 0, /* FLASHIO2 */ + 0, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 0, /* FLASHIO9 */ + 0, /* FLASHIO10 */ + 0, /* FLASHIO11 */ + 3, /* GENERALIO0 */ + 3, /* GENERALIO1 */ + 3, /* GENERALIO2 */ + 3, /* GENERALIO3 */ + 3, /* GENERALIO4 */ + 3, /* GENERALIO5 */ + 3, /* GENERALIO6 */ + 3, /* GENERALIO7 */ + 3, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 3, /* GENERALIO13 */ + 3, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 3, /* MIXED1IO0 */ + 3, /* MIXED1IO1 */ + 3, /* MIXED1IO2 */ + 3, /* MIXED1IO3 */ + 3, /* MIXED1IO4 */ + 3, /* MIXED1IO5 */ + 3, /* MIXED1IO6 */ + 3, /* MIXED1IO7 */ + 3, /* MIXED1IO8 */ + 3, /* MIXED1IO9 */ + 3, /* MIXED1IO10 */ + 3, /* MIXED1IO11 */ + 3, /* MIXED1IO12 */ + 3, /* MIXED1IO13 */ + 3, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 1, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h new file mode 100644 index 0000000000..f0c31860ca --- /dev/null +++ b/board/keymile/secu1/qts/pll_config.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 40000000 +#define CONFIG_HPS_CLK_OSC2_HZ 40000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 +#define CONFIG_HPS_CLK_USBCLK_HZ 12500000 +#define CONFIG_HPS_CLK_NAND_HZ 31250000 +#define CONFIG_HPS_CLK_SDMMC_HZ 3125000 +#define CONFIG_HPS_CLK_QSPI_HZ 3125000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h new file mode 100644 index 0000000000..b0ff86ef38 --- /dev/null +++ b/board/keymile/secu1/qts/sdram_config.h @@ -0,0 +1,327 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x11 +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x12 +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x14 +#define RW_MGR_CLEAR_DQS_ENABLE 0x4B +#define RW_MGR_EMR 0x09 +#define RW_MGR_EMR2 0x0D +#define RW_MGR_EMR3 0x0F +#define RW_MGR_EMR_OCD_ENABLE 0x0B +#define RW_MGR_GUARANTEED_READ 0x4E +#define RW_MGR_GUARANTEED_READ_CONT 0x56 +#define RW_MGR_GUARANTEED_WRITE 0x1A +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1D +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x21 +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1F +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x77 +#define RW_MGR_IDLE_LOOP2 0x76 +#define RW_MGR_INIT_CKE_0 0x71 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x27 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x26 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x34 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x23 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x3B +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x3A +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x48 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x37 +#define RW_MGR_MR_CALIB 0x05 +#define RW_MGR_MR_DLL_RESET 0x07 +#define RW_MGR_MR_USER 0x03 +#define RW_MGR_NOP 0x01 +#define RW_MGR_PRECHARGE_ALL 0x16 +#define RW_MGR_READ_B2B 0x5B +#define RW_MGR_READ_B2B_WAIT1 0x63 +#define RW_MGR_READ_B2B_WAIT2 0x6D +#define RW_MGR_REFRESH 0x18 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 301 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 6 +#define CALIB_VFIFO_OFFSET 4 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 416 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 74 +#define TINIT_CNTR1_VAL 20 +#define TINIT_CNTR2_VAL 20 +#define TRESET_CNTR0_VAL 74 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x30700000, + 0x38700000, + 0x30700000, + 0x20700000, + 0x10000853, + 0x10000853, + 0x10000953, + 0x10010000, + 0x10010380, + 0x10020000, + 0x10030000, + 0x10300400, + 0x10600000, + 0x10620000, + 0x10200400, + 0x10400000, + 0x1c900000, + 0x1c920000, + 0x1c900008, + 0x1c920008, + 0x38f00000, + 0x3cf00000, + 0x38700000, + 0x10100000, + 0x18900000, + 0x13500000, + 0x13520000, + 0x13500008, + 0x13520008, + 0x33700000, + 0x10500008 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80180, + 0x100, + 0x80000, + 0x200, + 0x80000, + 0x280, + 0x80000, + 0x300, + 0x80000, + 0x380, + 0x80000, + 0x400, + 0x80000, + 0x480, + 0x80000, + 0x500, + 0x80000, + 0x600, + 0x8000, + 0x680, + 0xa000, + 0x80000, + 0x700, + 0x80000, + 0x780, + 0x80000, + 0x968, + 0xcae8, + 0x8e8, + 0x8ae8, + 0x988, + 0xea88, + 0x808, + 0xaa88, + 0x80000, + 0xcc00, + 0xcb80, + 0xe080, + 0xa00, + 0x20ae0, + 0x20ae0, + 0x20ae0, + 0x20ae0, + 0xb00, + 0x0, + 0x0, + 0x0, + 0x0, + 0x60c80, + 0x60e80, + 0x60e80, + 0x60e80, + 0xa000, + 0x8000, + 0x80000, + 0xcc00, + 0xcb80, + 0xe080, + 0xa00, + 0x30ae0, + 0x30ae0, + 0x30ae0, + 0x30ae0, + 0xb00, + 0x0, + 0x0, + 0x0, + 0x0, + 0x70c80, + 0x70e80, + 0x70e80, + 0x70e80, + 0xa000, + 0x8000, + 0x80000, + 0xf58, + 0x58, + 0x80000, + 0xf68, + 0x168, + 0x168, + 0x8168, + 0x40de8, + 0x40ee8, + 0x40ee8, + 0x40ee8, + 0xf68, + 0x168, + 0x168, + 0xa168, + 0x80000, + 0x40c88, + 0x40e88, + 0x40e88, + 0x40e88, + 0x40d68, + 0x40ee8, + 0x40ee8, + 0x40ee8, + 0xa000, + 0x40de8, + 0x40ee8, + 0x40ee8, + 0x40ee8, + 0x40e08, + 0x40e88, + 0x40e88, + 0x40e88, + 0xf00, + 0xc000, + 0x8000, + 0xe000, + 0x80000, + 0x180, + 0x8180, + 0xa180, + 0xc180, + 0x80180, + 0x8000, + 0xa000, + 0x80000 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/keymile/secu1/socfpga.c b/board/keymile/secu1/socfpga.c new file mode 100644 index 0000000000..dc04a21abe --- /dev/null +++ b/board/keymile/secu1/socfpga.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2020 ABB + */ +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> + +#include "../common/common.h" + +/* + * For FU1, the MAC address associated with the mgmt port should + * be the base address (as read from the IVM) + 4, and for FU2 it + * is + 10 + */ +#define MAC_ADDRESS_OFFSET_FU1 4 +#define MAC_ADDRESS_OFFSET_FU2 10 + +/* + * This function reads the state of GPIO40 and returns true (non-zero) + * if it is '1' and false(0) otherwise. + * + * This pin is routed to a pull-up on FU2 and a pull-down on + */ +#define GPIO_FU_DETECTION 40 + +int secu1_is_fu2(void) +{ + int value; + int ret = gpio_request(GPIO_FU_DETECTION, "secu"); + + if (ret) { + printf("gpio: failed to request pin for FU detection\n"); + return 1; + } + gpio_direction_input(GPIO_FU_DETECTION); + value = gpio_get_value(GPIO_FU_DETECTION); + + if (value == 1) + printf("FU2 detected\n"); + else + printf("FU1 detected\n"); + + return value; +} + +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} +#endif + +int misc_init_r(void) +{ + if (secu1_is_fu2()) + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + MAC_ADDRESS_OFFSET_FU2); + else + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + MAC_ADDRESS_OFFSET_FU1); + + return 0; +} |