diff options
author | Tom Rini <trini@konsulko.com> | 2017-09-01 17:40:59 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-09-01 17:40:59 +0300 |
commit | 6aee2ab68c362ace5a59f89a63abed82e0bf19e5 (patch) | |
tree | 0b76045a178e9c0ed61e141bd8dfb3e34e4e86a9 /board | |
parent | 4109d702934c361b2ae2a5ad34f4dfee708cc214 (diff) | |
parent | 63af4b0ad0666e0797306593813b6272e1995bde (diff) | |
download | u-boot-6aee2ab68c362ace5a59f89a63abed82e0bf19e5.tar.xz |
Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/imx6qdl_icore_mmc_defconfig
configs/imx6qdl_icore_rqs_defconfig
Diffstat (limited to 'board')
-rw-r--r-- | board/bachmann/ot1200/ot1200.c | 11 | ||||
-rw-r--r-- | board/barco/platinum/platinum.h | 11 | ||||
-rw-r--r-- | board/congatec/cgtqmx6eval/cgtqmx6eval.c | 11 | ||||
-rw-r--r-- | board/el/el6x/el6x.c | 11 | ||||
-rw-r--r-- | board/engicam/common/spl.c | 22 | ||||
-rw-r--r-- | board/freescale/mx6sabreauto/mx6sabreauto.c | 17 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 17 | ||||
-rw-r--r-- | board/gateworks/gw_ventana/gw_ventana_spl.c | 11 | ||||
-rw-r--r-- | board/kosagi/novena/novena_spl.c | 11 | ||||
-rw-r--r-- | board/liebherr/mccmon6/spl.c | 11 | ||||
-rw-r--r-- | board/phytec/pcm058/pcm058.c | 12 | ||||
-rw-r--r-- | board/phytec/pfla02/Kconfig | 6 | ||||
-rw-r--r-- | board/phytec/pfla02/pfla02.c | 98 | ||||
-rw-r--r-- | board/solidrun/mx6cuboxi/mx6cuboxi.c | 11 | ||||
-rw-r--r-- | board/toradex/apalis_imx6/apalis_imx6.c | 24 | ||||
-rw-r--r-- | board/toradex/colibri_imx6/colibri_imx6.c | 24 | ||||
-rw-r--r-- | board/udoo/udoo_spl.c | 11 | ||||
-rw-r--r-- | board/wandboard/spl.c | 11 |
18 files changed, 97 insertions, 233 deletions
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index df10d6a0d0..9465cea72f 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -169,17 +169,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - int board_early_init_f(void) { ccgr_init(); diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h index d3ea8bda73..3013ed9078 100644 --- a/board/barco/platinum/platinum.h +++ b/board/barco/platinum/platinum.h @@ -75,15 +75,4 @@ static inline void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static inline void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - #endif /* _PLATINUM_H_ */ diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 8cd0090887..2ed66d3ba3 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -955,17 +955,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* Define a minimal structure so that the part number can be read via SPL */ struct mfgdata { unsigned char tsize; diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c index 6b98b5c3eb..fb128f5d4c 100644 --- a/board/el/el6x/el6x.c +++ b/board/el/el6x/el6x.c @@ -570,17 +570,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* * This section requires the differentiation between iMX6 Sabre boards, but * for now, it will configure only for the mx6q variant. diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index a8a7cf317e..6964c131d9 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -39,6 +39,17 @@ static iomux_v3_cfg_t const uart_pads[] = { #endif }; +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif + #ifdef CONFIG_MX6QDL /* * Driving strength: @@ -332,17 +343,6 @@ static void ccgr_init(void) #endif } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { #ifdef CONFIG_MX6QDL diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index f8f77f616c..15ca0294f5 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -798,23 +798,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - if (is_mx6dqp()) { - /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ - writel(0x77177717, &iomux->gpr[6]); - writel(0x77177717, &iomux->gpr[7]); - } else { - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); - } -} - static int mx6q_dcd_table[] = { 0x020e0798, 0x000C0000, 0x020e0758, 0x00000000, diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 9a562b3424..5b50bc815f 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -747,23 +747,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - if (is_mx6dqp()) { - /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ - writel(0x77177717, &iomux->gpr[6]); - writel(0x77177717, &iomux->gpr[7]); - } else { - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); - } -} - static int mx6q_dcd_table[] = { 0x020e0798, 0x000C0000, 0x020e0758, 0x00000000, diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9524da7daf..c2e370ba0b 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -583,17 +583,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 3645b75cb2..512f06da76 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -550,17 +550,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index 15844ef437..a2f804db8f 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -260,17 +260,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6SOLO)) { diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index 4257fbcb68..1538158987 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -487,18 +487,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - - static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig index 142a1222fc..f4da68b5ba 100644 --- a/board/phytec/pfla02/Kconfig +++ b/board/phytec/pfla02/Kconfig @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "pfla02" +config SPL_DRAM_1_BANK + bool "DRAM on just one bank" + help + activate, if the module has just one bank + of RAM + endif diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c index 8d2ce63e06..136f1d5e70 100644 --- a/board/phytec/pfla02/pfla02.c +++ b/board/phytec/pfla02/pfla02.c @@ -485,9 +485,9 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = { /* Index in RAM Chip array */ enum { - RAM_1GB, - RAM_2GB, - RAM_4GB + RAM_MT64K, + RAM_MT128K, + RAM_MT256K }; static struct mx6_ddr3_cfg mt41k_xx[] = { @@ -550,42 +550,11 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) +static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo, + struct mx6_ddr3_cfg *mem_ddr) { - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - -static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr) -{ - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 2, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr); + mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr); } int board_mmc_init(bd_t *bis) @@ -627,10 +596,12 @@ void board_boot_order(u32 *spl_boot_list) * Function checks for mirrors in the first CS */ #define RAM_TEST_PATTERN 0xaa5555aa -static unsigned int pfla02_detect_ramsize(void) +#define MIN_BANK_SIZE (512 * 1024 * 1024) + +static unsigned int pfla02_detect_chiptype(void) { u32 *p, *p1; - unsigned int offset = 512 * 1024 * 1024; + unsigned int offset = MIN_BANK_SIZE; int i; for (i = 0; i < 2; i++) { @@ -649,12 +620,38 @@ static unsigned int pfla02_detect_ramsize(void) if (*p == *p1) return i; } - return RAM_4GB; + return RAM_MT256K; } void board_init_f(ulong dummy) { unsigned int ramchip; + + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 512 MB */ + /* single chip select */ +#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) + .ncs = 1, +#else + .ncs = 2, +#endif + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); @@ -682,10 +679,23 @@ void board_init_f(ulong dummy) setup_gpios(); /* DDR initialization */ - spl_dram_init(&mt41k_xx[RAM_4GB]); - ramchip = pfla02_detect_ramsize(); - if (ramchip != RAM_4GB) - spl_dram_init(&mt41k_xx[ramchip]); + spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); + ramchip = pfla02_detect_chiptype(); + debug("Detected chip %d\n", ramchip); +#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) + switch (ramchip) { + case RAM_MT64K: + sysinfo.cs_density = 6; + break; + case RAM_MT128K: + sysinfo.cs_density = 10; + break; + case RAM_MT256K: + sysinfo.cs_density = 18; + break; + } +#endif + spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 7e59fb259e..986abc5772 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -581,17 +581,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(int width) { struct mx6_ddr_sysinfo sysinfo = { diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 7a3e493faf..ebc6c12cbc 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -29,6 +29,7 @@ #include <dm/platform_data/serial_mxc.h> #include <dm/platdata.h> #include <fsl_esdhc.h> +#include <g_dnl.h> #include <i2c.h> #include <imx_thermal.h> #include <linux/errno.h> @@ -1159,17 +1160,6 @@ static void ccgr_init(void) writel(0x000000FB, &ccm->ccosr); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void ddr_init(int *table, int size) { int i; @@ -1234,6 +1224,18 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_SPL_USB_GADGET_SUPPORT +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + unsigned short usb_pid; + + usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff; + put_unaligned(usb_pid, &dev->idProduct); + + return 0; +} +#endif + #endif static struct mxc_serial_platdata mxc_serial_plat = { diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index dbcd233782..669d9123ca 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -28,6 +28,7 @@ #include <dm/platform_data/serial_mxc.h> #include <dm/platdata.h> #include <fsl_esdhc.h> +#include <g_dnl.h> #include <i2c.h> #include <imx_thermal.h> #include <linux/errno.h> @@ -1036,17 +1037,6 @@ static void ccgr_init(void) writel(0x000000FB, &ccm->ccosr); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void ddr_init(int *table, int size) { int i; @@ -1118,6 +1108,18 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_SPL_USB_GADGET_SUPPORT +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + unsigned short usb_pid; + + usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff; + put_unaligned(usb_pid, &dev->idProduct); + + return 0; +} +#endif + #endif static struct mxc_serial_platdata mxc_serial_plat = { diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index e83e7c3a1b..3645969e43 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -211,17 +211,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000FF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6DL)) { diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 47082a88d5..99a02865ec 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -266,17 +266,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6SOLO)) { |