board: starfive: Support visionfive2

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>

7 files changed, 380 insertions, 160 deletions

diff --git a/board/starfive/visionfive/MAINTAINERS b/board/starfive/visionfive/MAINTAINERS
deleted file mode 100644
index 437f6c2d24..0000000000
--- a/board/starfive/visionfive/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-STARFIVE JH7110 VISIONFIVE BOARD
-M: startfive
-S:	Maintained
-F:	arch/riscv/include/asm/arch-jh7110/
-F:	board/starfive/visionfive/
-F:	include/configs/starfive-visionfive.h
-F:	configs/starfive_visionfive_defconfig
diff --git a/board/starfive/visionfive/spl.c b/board/starfive/visionfive/spl.c
deleted file mode 100644
index d74ecb9690..0000000000
--- a/board/starfive/visionfive/spl.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 Starfive, Inc.
- * Author:	yanhong <yanhong.wang@starfivetech.com>
- *
- */
-
-#include <common.h>
-#include <init.h>
-#include <spl.h>
-#include <log.h>
-#include <linux/delay.h>
-#include <image.h>
-#include <asm/arch/spl.h>
-#include <asm/io.h>
-
-#define MODE_SELECT_REG		0x1702002c
-
-int spl_board_init_f(void)
-{
-	int ret;
-
-	ret = spl_soc_init();
-	if (ret) {
-		debug("JH7110 SPL init failed: %d\n", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-u32 spl_boot_device(void)
-{
-	int boot_mode = 0;
-
-	boot_mode = readl((const volatile void *)MODE_SELECT_REG) & 0xF;
-	switch (boot_mode) {
-	case 0:
-		return BOOT_DEVICE_SPI;
-	case 1:
-		return BOOT_DEVICE_MMC2;
-	case 2:
-		return BOOT_DEVICE_MMC1;
-	case 4:
-		return BOOT_DEVICE_UART;
-	default:
-		debug("Unsupported boot device 0x%x.\n",
-		      boot_mode);
-		return BOOT_DEVICE_NONE;
-	}
-}
-
-struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
-{
-	return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
-}
-
-void board_init_f(ulong dummy)
-{
-	int ret;
-
-	ret = spl_early_init();
-	if (ret)
-		panic("spl_early_init() failed: %d\n", ret);
-
-	arch_cpu_init_dm();
-
-	preloader_console_init();
-
-	ret = spl_board_init_f();
-	if (ret) {
-		debug("spl_board_init_f init failed: %d\n", ret);
-		return;
-	}
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* boot using first FIT config */
-	return 0;
-}
-#endif
-
-
diff --git a/board/starfive/visionfive/Kconfig b/board/starfive/visionfive2/Kconfig
index d0ed065307..28bde2a09b 100644
--- a/board/starfive/visionfive/Kconfig
+++ b/board/starfive/visionfive2/Kconfig
@@ -1,16 +1,16 @@
-if TARGET_STARFIVE_VISIONFIVE
+if TARGET_STARFIVE_VISIONFIVE2
 
 config SYS_CPU
 	default "jh7110"
 
 config SYS_BOARD
-	default "visionfive"
+	default "visionfive2"
 
 config SYS_VENDOR
 	default "starfive"
 
 config SYS_CONFIG_NAME
-	default "starfive-visionfive"
+	default "starfive-visionfive2"
 
 config ENV_SIZE
 	default 0x2000 if ENV_IS_IN_SPI_FLASH
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 0000000000..c5369086d8
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S:	Maintained
+F:	arch/riscv/include/asm/arch-jh7110/
+F:	board/starfive/visionfive2/
+F:	include/configs/starfive-visionfive2.h
+F:	configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive/Makefile b/board/starfive/visionfive2/Makefile
index 739370cb2a..219d3de7ed 100644
--- a/board/starfive/visionfive/Makefile
+++ b/board/starfive/visionfive2/Makefile
@@ -3,7 +3,7 @@
 # Copyright (C) 2021 Shanghai StarFive Technology Co., Ltd.
 #
 
-obj-y	:= starfive_visionfive.o
+obj-y	:= starfive_visionfive2.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o
 
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 0000000000..6ba7fc7cc3
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Starfive, Inc.
+ * Author:	yanhong <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/arch/spl.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/jh7110-regs.h>
+#include <image.h>
+#include <linux/bitops.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <spl.h>
+
+#define MODE_SELECT_REG		0x1702002c
+
+struct starfive_pll0_freq {
+	u32 freq;
+	u32 prediv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 dacpd; /* Both daxpd and dsmpd set 1 while integer multiple mode */
+	u32 dsmpd; /* Both daxpd and dsmpd set 0 while fraction multiple mode */
+};
+
+enum starfive_cpu_freq {
+	CPU_FREQ_375 = 0,
+	CPU_FREQ_500,
+	CPU_FREQ_625,
+	CPU_FREQ_750,
+	CPU_FREQ_875,
+	CPU_FREQ_1000,
+	CPU_FREQ_1250,
+	CPU_FREQ_1375,
+	CPU_FREQ_1500,
+	CPU_FREQ_1625,
+	CPU_FREQ_1750,
+	CPU_FREQ_1800,
+	CPU_FREQ_MAX = CPU_FREQ_1800
+};
+
+struct starfive_pll0_freq jh7110_pll0_freq[] = {
+	{
+		.freq = CPU_FREQ_375,
+		.prediv = 8,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_500,
+		.prediv = 6,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_625,
+		.prediv = 24,
+		.fbdiv = 625,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_750,
+		.prediv = 4,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_875,
+		.prediv = 24,
+		.fbdiv = 875,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1000,
+		.prediv = 3,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1250,
+		.prediv = 12,
+		.fbdiv = 625,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1375,
+		.prediv = 24,
+		.fbdiv = 1375,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1500,
+		.prediv = 2,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1625,
+		.prediv = 24,
+		.fbdiv = 1625,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1750,
+		.prediv = 12,
+		.fbdiv = 875,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+	{
+		.freq = CPU_FREQ_1800,
+		.prediv = 3,
+		.fbdiv = 225,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1
+	},
+};
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("JH7110 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	int boot_mode = 0;
+
+	boot_mode = readl((const volatile void *)MODE_SELECT_REG) & 0x3;
+	switch (boot_mode) {
+	case 0:
+		return BOOT_DEVICE_SPI;
+	case 1:
+		return BOOT_DEVICE_MMC2;
+	case 2:
+		return BOOT_DEVICE_MMC1;
+	case 3:
+		return BOOT_DEVICE_UART;
+	default:
+		debug("Unsupported boot device 0x%x.\n",
+		      boot_mode);
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
+}
+
+static int spl_cpu_set_rate(enum starfive_cpu_freq rate)
+{
+	struct starfive_pll0_freq *cpu_freq;
+	int i;
+
+	if (rate < 0 || rate > CPU_FREQ_MAX) {
+		debug("invalid input value=%d\n", rate);
+		return -EINVAL;
+	}
+
+	for (i = 0; i<CPU_FREQ_MAX; i++) {
+		if (jh7110_pll0_freq[i].freq == rate) {
+			cpu_freq = &jh7110_pll0_freq[i];
+			break;
+		}
+	}
+
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
+		(cpu_freq->dacpd << PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
+		(cpu_freq->dsmpd << PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
+		(cpu_freq->prediv << PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
+		(cpu_freq->fbdiv << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
+		((cpu_freq->postdiv1 >> 1) << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Adjust cpu frequency, the default is 1.25GHz */
+	spl_cpu_set_rate(CPU_FREQ_1250);
+
+	/*DDR control depend clk init*/
+	clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
+		BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK);
+
+	clrsetbits_le32(SYS_CRG_BASE + CLK_BUS_ROOT_OFFSET,
+		CLK_BUS_ROOT_SW_MASK,
+		BIT(CLK_BUS_ROOT_SW_SHIFT) & CLK_BUS_ROOT_SW_MASK);
+
+	clrsetbits_le32(SYS_CRG_BASE + CLK_NOC_BUS_STG_AXI_OFFSET,
+		CLK_NOC_BUS_STG_AXI_EN_MASK,
+		BIT(CLK_NOC_BUS_STG_AXI_EN_SHIFT)
+		& CLK_NOC_BUS_STG_AXI_EN_MASK);
+
+	clrsetbits_le32(AON_CRG_BASE + CLK_AON_APB_FUNC_OFFSET,
+		CLK_AON_APB_FUNC_SW_MASK,
+		BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK);
+
+	clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
+		CLK_QSPI_REF_SW_MASK,
+		(0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
+
+	/*set GPIO to 3.3v*/
+	setbits_le32(SYS_SYSCON_BASE + 0xC, 0x0);
+
+	/*set sdio0 sdcard clk default div to 4*/
+	clrsetbits_le32(SYS_CRG_BASE + CLK_SDIO0_SDCARD_OFFSET,
+		CLK_SDIO0_SDCARD_MASK,
+		(4 << CLK_SDIO0_SDCARD_SHIFT) & CLK_SDIO0_SDCARD_MASK);
+
+	/* reset emmc */
+	SYS_IOMUX_DOEN(22, LOW);
+	SYS_IOMUX_DOUT(22, 19);
+	/* reset sdio */
+	SYS_IOMUX_DOEN(4, LOW);
+	SYS_IOMUX_DOUT(4, 55);
+	SYS_IOMUX_COMPLEX(5, 44, 57, 19);
+	SYS_IOMUX_COMPLEX(0, 45, 58, 20);
+	SYS_IOMUX_COMPLEX(1, 46, 59, 21);
+	SYS_IOMUX_COMPLEX(2, 47, 60, 22);
+	SYS_IOMUX_COMPLEX(3, 48, 61, 23);
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	arch_cpu_init_dm();
+
+	preloader_console_init();
+
+	ret = spl_board_init_f();
+	if (ret) {
+		debug("spl_board_init_f init failed: %d\n", ret);
+		return;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
+
+
diff --git a/board/starfive/visionfive/starfive_visionfive.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 7f9de3d9de..2bbacf32a9 100755
--- a/board/starfive/visionfive/starfive_visionfive.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -17,37 +17,17 @@
 #include <linux/bitops.h>
 #include <asm/arch/gpio.h>
 
-#define SYS_IOMUX_DOEN(gpio, oen) \
-	clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \
-		GPIO_DOEN_MASK <<  GPIO_SHIFT(gpio), \
-		(oen) << GPIO_SHIFT(gpio))
-
-#define SYS_IOMUX_DOUT(gpio, gpo) \
-	clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\
-		GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\
-		((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
-
-#define SYS_IOMUX_DIN(gpio, gpi)\
-	clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\
-		GPIO_DIN_MASK << GPIO_SHIFT(gpi),\
-		((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
-
-#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\
-	SYS_IOMUX_DOEN(gpio, oen);\
-	SYS_IOMUX_DOUT(gpio, gpo);\
-	SYS_IOMUX_DIN(gpio, gpi); }while(0)
-
 #define SYS_CLOCK_ENABLE(clk) \
 	setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
 
 static void sys_reset_clear(ulong assert, ulong status, u32 rst)
 {
-	volatile u32 value;
+	u32 value;
 
 	clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
-	do{
+	do {
 		value = in_le32(SYS_CRG_BASE + status);
-	}while((value & BIT(rst)) != BIT(rst));
+	} while ((value & BIT(rst)) != BIT(rst));
 }
 
 static void jh7110_timer_init(void)
@@ -90,47 +70,82 @@ static void jh7110_gmac_init(int id)
 	}
 }
 
-static void jh7110_usb_init(void)
+static void jh7110_usb_init(bool usb2_enable)
 {
-	clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_4,
-		USB_MODE_STRAP_MASK,
-		(2<<USB_MODE_STRAP_SHIFT) & USB_MODE_STRAP_MASK);
-	clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
-		USB_OTG_SUSPENDM_BYPS_MASK,
-		BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
-		& USB_OTG_SUSPENDM_BYPS_MASK);
-
-	clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
-		USB_OTG_SUSPENDM_MASK,
-		BIT(USB_OTG_SUSPENDM_SHIFT) & USB_OTG_SUSPENDM_MASK);
-	clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
-		USB_PLL_EN_MASK,
-		BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
-	clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
-		USB_REFCLK_MODE_MASK,
-		BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
-
-	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
-		PDRSTN_SPLIT_MASK,
-		BIT(PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
-	clrsetbits_le32(SYS_IOMUX_BASE + SYS_IOMUX_32,
-		IOMUX_USB_MASK,
-		BIT(IOMUX_USB_SHIFT) & IOMUX_USB_MASK);
+	if (usb2_enable) {
+		/*usb 2.0 utmi phy init*/
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_4,
+			USB_MODE_STRAP_MASK,
+			(2<<USB_MODE_STRAP_SHIFT) &
+			USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
+		clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
+			USB_OTG_SUSPENDM_BYPS_MASK,
+			BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
+			& USB_OTG_SUSPENDM_BYPS_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
+			USB_OTG_SUSPENDM_MASK,
+			BIT(USB_OTG_SUSPENDM_SHIFT) &
+			USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
+		clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
+			USB_PLL_EN_MASK,
+			BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
+			USB_REFCLK_MODE_MASK,
+			BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
+		/* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
+		clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
+			PDRSTN_SPLIT_MASK,
+			BIT(PDRSTN_SPLIT_SHIFT) &
+			PDRSTN_SPLIT_MASK);
+	} else {
+		/*usb 3.0 pipe phy config*/
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_196,
+			PCIE_CKREF_SRC_MASK,
+			(0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_196,
+			PCIE_CLK_SEL_MASK,
+			(0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_328,
+			PCIE_PHY_MODE_MASK,
+			BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_500,
+			PCIE_USB3_BUS_WIDTH_MASK,
+			(0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
+			PCIE_USB3_BUS_WIDTH_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_500,
+			PCIE_USB3_RATE_MASK,
+			(0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_500,
+			PCIE_USB3_RX_STANDBY_MASK,
+			(0 << PCIE_USB3_RX_STANDBY_SHIFT)
+			& PCIE_USB3_RX_STANDBY_MASK);
+		clrsetbits_le32(STG_SYSCON_BASE  + STG_SYSCON_500,
+			PCIE_USB3_PHY_ENABLE_MASK,
+			BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
+			& PCIE_USB3_PHY_ENABLE_MASK);
+
+		/* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
+		clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
+			PDRSTN_SPLIT_MASK,
+			(0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
+	}
+	SYS_IOMUX_DOEN(25, LOW);
+	SYS_IOMUX_DOUT(25, 7);
 }
 
 static void jh7110_mmc_init(int id)
 {
 	if (id == 0) {
-		SYS_IOMUX_DOEN(62, LOW);
-		SYS_IOMUX_DOUT(62, 19);
+		SYS_IOMUX_DOEN(22, LOW);
+		SYS_IOMUX_DOUT(22, 19);
 	} else {
-		SYS_IOMUX_DOEN(10, LOW);
-		SYS_IOMUX_DOUT(10, 55);
-		SYS_IOMUX_COMPLEX(9, 44, 57, 19);
-		SYS_IOMUX_COMPLEX(11, 45, 58, 20);
-		SYS_IOMUX_COMPLEX(12, 46, 59, 21);
-		SYS_IOMUX_COMPLEX(7, 47, 60, 22);
-		SYS_IOMUX_COMPLEX(8, 48, 61, 23);
+		SYS_IOMUX_DOEN(4, LOW);
+		SYS_IOMUX_DOUT(4, 55);
+		SYS_IOMUX_COMPLEX(5, 44, 57, 19);
+		SYS_IOMUX_COMPLEX(0, 45, 58, 20);
+		SYS_IOMUX_COMPLEX(1, 46, 59, 21);
+		SYS_IOMUX_COMPLEX(2, 47, 60, 22);
+		SYS_IOMUX_COMPLEX(3, 48, 61, 23);
 	}
 }
 
@@ -158,13 +173,13 @@ int board_init(void)
 	enable_caches();
 
 	/*enable hart1-hart4 prefetcher*/
-//	enable_prefetcher();
+	enable_prefetcher();
 
 	jh7110_gmac_init(0);
 	jh7110_gmac_init(1);
 	jh7110_timer_init();
 
-	jh7110_usb_init();
+	jh7110_usb_init(true);
 
 	jh7110_mmc_init(0);
 	jh7110_mmc_init(1);
@@ -176,11 +191,12 @@ int board_init(void)
 
 int misc_init_r(void)
 {
-	char mac[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad };
+	char mac0[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad};
+	char mac1[6] = {0x66, 0x34, 0xb0, 0x7c, 0xae, 0x5d};
 
 #if CONFIG_IS_ENABLED(STARFIVE_OTP)
 	struct udevice *dev;
-	char buf[8];
+	char buf[16];
 	int ret;
 #define MACADDR_OFFSET 0x8
 
@@ -195,11 +211,14 @@ int misc_init_r(void)
 	if (ret)
 		printf("%s: error reading mac from OTP\n", __func__);
 	else
-		if (buf[0] != 0xff)
-			memcpy(mac, buf, 6);
+		if (buf[0] != 0xff) {
+			memcpy(mac0, buf, 6);
+			memcpy(mac1, &buf[8], 6);
+		}
 err:
 #endif
-	eth_env_set_enetaddr("ethaddr", mac);
+	eth_env_set_enetaddr("eth0addr", mac0);
+	eth_env_set_enetaddr("eth1addr", mac1);
 
 	return 0;
 }