diff options
author | Stefan Roese <sr@denx.de> | 2010-10-25 20:32:08 +0400 |
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committer | Stefan Roese <sr@denx.de> | 2010-12-17 11:43:23 +0300 |
commit | cf1971c1c0a76c3105a347102db083027a3d7b91 (patch) | |
tree | 7699cbd85d0deb7204ecfc08002a9777471744d3 /board | |
parent | 97a85b223ab316d11f3a374fecc5d449a1c8a694 (diff) | |
download | u-boot-cf1971c1c0a76c3105a347102db083027a3d7b91.tar.xz |
ppc4xx: t3corp: Add support for the Xilinx DS617 flash chip
The t3corp board has an Xilinx DS617 flash chip connected to the
onboard FPGA. This patch adds support for these chips. Board
specific flash accessor functions are needed, since the chips
can only be read correctly in 16bit mode.
Additionally the FPGA chip-selects are configured for device-paced
transfers (ready is enabled).
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
-rw-r--r-- | board/t3corp/t3corp.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c index 04d6a2e2af..f2853e42e5 100644 --- a/board/t3corp/t3corp.c +++ b/board/t3corp/t3corp.c @@ -23,6 +23,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <i2c.h> +#include <mtd/cfi_flash.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> @@ -191,3 +192,40 @@ struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val) { return board_scan_options; } + +/* + * Accessor functions replacing the "weak" functions in + * drivers/mtd/cfi_flash.c + * + * The NOR flash devices "behind" the FPGA's (Xilinx DS617) + * can only be read correctly in 16bit mode. We need to emulate + * 8bit and 32bit reads here in the board specific code. + */ +u8 flash_read8(void *addr) +{ + u16 val = __raw_readw((void *)((u32)addr & ~1)); + + if ((u32)addr & 1) + return val; + + return val >> 8; +} + +u32 flash_read32(void *addr) +{ + return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2)); +} + +void flash_cmd_reset(flash_info_t *info) +{ + /* + * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and + * needs the Spansion type reset commands. The other flash chip + * is located behind a FPGA (Xilinx DS617) and needs the Intel type + * reset command. + */ + if (info->start[0] == CONFIG_SYS_FLASH_BASE) + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + else + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); +} |