Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.10
----------------

- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785

15 files changed, 92 insertions, 427 deletions

diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c
index e82e8b78d8..c61d25fbea 100644
--- a/board/beacon/imx8mm/imx8mm_beacon.c
+++ b/board/beacon/imx8mm/imx8mm_beacon.c
@@ -13,17 +13,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_FEC_MXC)
 static int setup_fec(void)
 {
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
index c43af9bc48..6af7100696 100644
--- a/board/freescale/imx8mm_evk/imx8mm_evk.c
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -15,17 +15,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_FEC_MXC)
 static int setup_fec(void)
 {
diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c
index ea02bb75f4..e5ca54f9ae 100644
--- a/board/freescale/imx8mn_evk/imx8mn_evk.c
+++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -9,13 +9,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 int board_init(void)
 {
 	return 0;
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 97ba15645a..034a349236 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -40,46 +40,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->ram_size = PHYS_SDRAM_SIZE;
-
-#if CONFIG_NR_DRAM_BANKS > 1
-	gd->ram_size += PHYS_SDRAM_2_SIZE;
-#endif
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	if (rom_pointer[1])
-
-		gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
-
-#if CONFIG_NR_DRAM_BANKS > 1
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-
-	return 0;
-}
-
-phys_size_t get_effective_memsize(void)
-{
-	if (rom_pointer[1])
-		return (PHYS_SDRAM_SIZE - rom_pointer[1]);
-	else
-		return PHYS_SDRAM_SIZE;
-}
-
 int board_init(void)
 {
 	return 0;
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 14542490bc..7658262b37 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -11,7 +11,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400304, 0x1 },
 	{ 0x3d400030, 0x1 },
 	{ 0x3d400000, 0xa3080020 },
-	{ 0x3d400020, 0x323 },
+	{ 0x3d400020, 0x1323 },
 	{ 0x3d400024, 0x1e84800 },
 	{ 0x3d400064, 0x7a0118 },
 	{ 0x3d4000d0, 0xc00307a3 },
@@ -52,12 +52,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x68070707 },
 	{ 0x3d40021c, 0xf08 },
-	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400250, 0x00001705 },
 	{ 0x3d400254, 0x2c },
 	{ 0x3d40025c, 0x4000030 },
 	{ 0x3d400264, 0x900093e7 },
 	{ 0x3d40026c, 0x2005574 },
 	{ 0x3d400400, 0x111 },
+       { 0x3d400404, 0x72ff },
 	{ 0x3d400408, 0x72ff },
 	{ 0x3d400494, 0x2100e07 },
 	{ 0x3d400498, 0x620096 },
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index 3b3a854e29..3214718e62 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -68,7 +68,7 @@ int power_init_board(void)
 	struct pmic *p;
 	int ret;
 
-	ret = power_pca9450b_init(I2C_PMIC);
+	ret = power_pca9450_init(I2C_PMIC);
 	if (ret)
 		printf("power init failed");
 	p = pmic_get("PCA9450");
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index ae3be5785c..1ad670b8cc 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -53,17 +53,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {
diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c
index c0cc3e9b71..746071b415 100644
--- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c
+++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c
@@ -48,17 +48,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {
diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c
index 8159f3a2d9..4062c6fb82 100644
--- a/board/liebherr/xea/xea.c
+++ b/board/liebherr/xea/xea.c
@@ -116,6 +116,7 @@ void board_boot_order(u32 *spl_boot_list)
 {
 	spl_boot_list[0] = BOOT_DEVICE_MMC1;
 	spl_boot_list[1] = BOOT_DEVICE_SPI;
+	spl_boot_list[2] = BOOT_DEVICE_UART;
 }
 
 int spl_start_uboot(void)
diff --git a/board/phytec/pcm058/MAINTAINERS b/board/phytec/pcm058/MAINTAINERS
index b0ca40277f..909dfc44af 100644
--- a/board/phytec/pcm058/MAINTAINERS
+++ b/board/phytec/pcm058/MAINTAINERS
@@ -1,6 +1,7 @@
 PHYTEC PHYBOARD MIRA
-M:	Stefano Babic <sbabic@denx.de>
+M:	Niel Fourie <lusus@denx.de>
 S:	Maintained
 F:	board/phytec/pcm058/
 F:	include/configs/pcm058.h
 F:	configs/pcm058_defconfig
+F:	arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi
diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README
index 3327135645..02be0994fc 100644
--- a/board/phytec/pcm058/README
+++ b/board/phytec/pcm058/README
@@ -33,3 +33,54 @@ is present, then the RBL tries to load SPL from the SD Card, if not,
 RBL loads from SPI-NOR. The SPL tries then to load from the same
 device where SPL was loaded (SD or SPI). Booting from NAND is
 not supported.
+
+Flashing U-Boot onto an SD card
+-------------------------------
+
+After a successful build, the generated SPL and U-boot binaries can be copied
+to an SD card. Adjust the SD card device as necessary:
+
+$ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1
+
+This is equivalent to separately copying the SPL and U-boot using:
+
+$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1
+$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197
+
+The default bootscripts expect a kernel fit-image file named "fitImage" in the
+first partition and Linux ext4 rootfs in the second partition.
+
+Flashing U-boot to the SPI Flash, for booting Linux from NAND
+-------------------------------------------------------------
+
+The SD card created above can also be used to install the SPL and U-boot into
+the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot.
+
+Then, clear the SPI flash:
+
+=> sf probe
+=> sf erase 0x0 0x1000000
+
+Load the SPL from raw MMC into memory and copy to the SPI. The SPL is maximum
+392*512-byte blocks in size therefore 0x188 blocks, totaling 0x31000 bytes:
+
+=> mmc read ${loadaddr} 0x2 0x188
+=> sf write ${loadaddr} 0x400 0x31000
+
+Load the U-boot binary into memory and copy to the SPI. U-boot should fit into
+640KiB, so 0x500 512-byte blocks, totalling 0xA0000 bytes:
+
+=> mmc read ${loadaddr} 0x18a 0x500
+=> sf write ${loadaddr} 0x40000 0xA0000
+
+The default NAND bootscripts expect a single MTD partition named "rootfs",
+which in turn contains the UBI volumes "fit" (which contains the kernel fit-
+image) and "root" (which contains a ubifs root filesystem).
+
+The "bootm_size" variable in the environment
+--------------------------------------------
+
+By default, U-boot relocates the device tree towards the upper end of the RAM,
+which kernels using CONFIG_HIGHMEM=y may not be able to access during early
+boot. With the bootm_size variable set to 0x30000000, U-boot relocates the
+device tree to below this address instead.
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 096425c5df..79c666588f 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -12,60 +12,14 @@
 #include <common.h>
 #include <init.h>
 #include <net.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/mx6-ddr.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <mmc.h>
-#include <i2c.h>
-#include <fsl_esdhc_imx.h>
-#include <nand.h>
-#include <miiphy.h>
-#include <netdev.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/sections.h>
+#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |	\
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-	       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(6, 31)
-#define USER_LED	IMX_GPIO_NR(1, 4)
 #define IMX6Q_DRIVE_STRENGTH	0x30
 
 int dram_init(void)
@@ -74,229 +28,16 @@ int dram_init(void)
 	return 0;
 }
 
-void board_turn_off_led(void)
-{
-	gpio_direction_output(USER_LED, 0);
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__GPIO1_IO14	| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#ifdef CONFIG_CMD_NAND
-/* NAND */
-static iomux_v3_cfg_t const nfc_pads[] = {
-	MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_CS2__NAND_CE2_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_CS3__NAND_CE3_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NAND_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
-};
-#endif
-
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 5)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
-	{.esdhc_base = USDHC1_BASE_ADDR,
-	.max_bus_width = 4},
-#ifndef CONFIG_CMD_NAND
-	{USDHC4_BASE_ADDR},
-#endif
-};
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-#endif
-
 int board_mmc_get_env_dev(int devno)
 {
 	return devno - 1;
 }
 
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = 1; /* eMMC/uSDHC4 is always present */
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
-	int ret;
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			gpio_direction_input(USDHC1_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-#ifndef CONFIG_CMD_NAND
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-#endif
-		default:
-			printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-#else
-	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-	unsigned reg = readl(&psrc->sbmr1) >> 11;
-	/*
-	 * Upon reading BOOT_CFG register the following map is done:
-	 * Bit 11 and 12 of BOOT_CFG register can determine the current
-	 * mmc port
-	 * 0x1                  SD1
-	 * 0x2                  SD2
-	 * 0x3                  SD4
-	 */
-
-	switch (reg & 0x3) {
-	case 0x0:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-		gpio_direction_input(USDHC1_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-		usdhc_cfg[0].max_bus_width = 4;
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	}
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
-	gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
-	mdelay(10);
-	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
-	mdelay(30);
-}
-
-static void setup_spi(void)
-{
-	gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
-	gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
-
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-
-	enable_spi_clk(true, 0);
-}
-
 #ifdef CONFIG_CMD_NAND
 static void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
-
 	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
 	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 
@@ -325,48 +66,17 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	if (bus != 0 || (cs != 0))
-		return -EINVAL;
-
-	return IMX_GPIO_NR(3, 19);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	setup_iomux_enet();
-
-	return cpu_eth_init(bis);
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-	return 0;
-}
-
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
-
-#ifdef CONFIG_MXC_SPI
-	setup_spi();
-#endif
-
 #ifdef CONFIG_CMD_NAND
 	setup_gpmi_nand();
 #endif
 	return 0;
 }
 
-
 #ifdef CONFIG_CMD_BMODE
 /*
  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
@@ -535,11 +245,6 @@ void board_boot_order(u32 *spl_boot_list)
 
 void board_init_f(ulong dummy)
 {
-#ifdef CONFIG_CMD_NAND
-	/* Enable NAND */
-	setup_gpmi_nand();
-#endif
-
 	/* setup clock gating */
 	ccgr_init();
 
@@ -549,23 +254,33 @@ void board_init_f(ulong dummy)
 	/* setup AXI */
 	gpr_init();
 
-	board_early_init_f();
-
 	/* setup GP timer */
 	timer_init();
 
-	setup_spi();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
 	/* DDR initialization */
 	spl_dram_init();
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
+	/* Enable device tree and early DM support*/
+	spl_early_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+}
+
+/*
+ *  Manually probe the SPI bus devices, as this does not happen when the
+ *  SPI Flash is probed, which then fails to find the bus.
+ */
+void spl_board_init(void)
+{
+	struct udevice *udev;
+	int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev);
+
+	if (ret) {
+		printf("SPI bus probe failed, err = %d\n", ret);
+	};
 }
 #endif
diff --git a/board/technexion/pico-imx6ul/README b/board/technexion/pico-imx6ul/README
index 40d4344142..e58640c55e 100644
--- a/board/technexion/pico-imx6ul/README
+++ b/board/technexion/pico-imx6ul/README
@@ -22,8 +22,8 @@ If the eMMC has already a U-Boot flashed with DFU support then
 the user can go to step 2 below in order to update U-Boot.
 
 Put pico board in USB download mode (refer to the document
-http://www.wandboard.org/images/hobbit/hobbitboard-imx6ul-reva1.pdf
-page 15).
+https://www.nxp.com/files-static/32bit/doc/quick_start_guide/PICO-IMX6UL-QSG.pdf
+Figure 6a at page 7).
 
 Connect a USB to serial adapter between the host PC and pico.
 
diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c
index 2a3e6e7e26..330de7137c 100644
--- a/board/technexion/pico-imx8mq/pico-imx8mq.c
+++ b/board/technexion/pico-imx8mq/pico-imx8mq.c
@@ -51,24 +51,22 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int dram_init(void)
+int board_phys_sdram_size(phys_size_t *size)
 {
 	int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
 
-	if (ddr_size == 0x4)
-		gd->ram_size = 0x100000000;
-	else if (ddr_size == 0x3)
-		gd->ram_size = 0xc0000000;
-	else if (ddr_size == 0x2)
-		gd->ram_size = 0x80000000;
-	else if (ddr_size == 0x1)
-		gd->ram_size = 0x40000000;
-	else
+	if (ddr_size == 0x4) {
+		*size = 0x100000000;
+	} else if (ddr_size == 0x3) {
+		*size = 0xc0000000;
+	} else if (ddr_size == 0x2) {
+		*size = 0x80000000;
+	} else if (ddr_size == 0x1) {
+		*size = 0x40000000;
+	} else {
 		printf("Unknown DDR type!!!\n");
-
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size -= rom_pointer[1];
+		return -1;
+	}
 
 	return 0;
 }
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index ff05c7d552..fa51b776ab 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -14,17 +14,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
-		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
-	else
-		gd->ram_size = PHYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 #if IS_ENABLED(CONFIG_FEC_MXC)
 static int setup_fec(void)
 {