global: Finish CONFIG -> CFG migration

At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

23 files changed, 61 insertions, 61 deletions

diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index 0cfb7c522f..80ad62c2c6 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define MVEBU_DEV_BUS_BASE		(MVEBU_REGISTER(0x10400))
 
-#define CONFIG_NVS_LOCATION		0xf4800000
-#define CONFIG_NVS_SIZE			(512 << 10)
+#define CFG_NVS_LOCATION		0xf4800000
+#define CFG_NVS_SIZE			(512 << 10)
 
 static struct serdes_map board_serdes_map[] = {
 	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
@@ -109,7 +109,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
 	/* window for NVS */
-	mbus_dt_setup_win(CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
+	mbus_dt_setup_win(CFG_NVS_LOCATION, CFG_NVS_SIZE,
 			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
 
 	/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 99fb67eced..ee65a59683 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -220,7 +220,7 @@ int board_eth_init(struct bd_info *bis)
 	int rc = 0;
 #ifndef CONFIG_DM_ETH
 #ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	rc = smc911x_initialize(0, CFG_SMC911X_BASE);
 #endif
 #endif
 	return rc;
diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
index 4dbd847d42..90cc33a6e4 100644
--- a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
@@ -12,7 +12,7 @@
 
 #ifdef CONFIG_SPL_BUILD
 
-#define CONFIG_SYS_I2C_EEPROM_ADDR_P1	0x51
+#define CFG_SYS_I2C_EEPROM_ADDR_P1	0x51
 
 static iomux_v3_cfg_t const eeprom_pads[] = {
 	IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -40,7 +40,7 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len)
 	struct udevice *dev;
 	int ret;
 
-	ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+	ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
 	if (ret) {
 		printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
@@ -57,7 +57,7 @@ static int cl_eeprom_write(uint offset, uchar *buf, int len)
 
 	cl_eeprom_we(1);
 
-	ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+	ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
 	if (ret) {
 		printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index e3a0f266a4..474dca7292 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -226,8 +226,8 @@ const struct lpsc_resource lpsc[] = {
 
 const int lpsc_size = ARRAY_SIZE(lpsc);
 
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
+#ifndef CFG_DA850_EVM_MAX_CPU_CLK
+#define CFG_DA850_EVM_MAX_CPU_CLK	300000000
 #endif
 
 #define REV_AM18X_EVM		0x100
@@ -245,7 +245,7 @@ const int lpsc_size = ARRAY_SIZE(lpsc);
 u32 get_board_rev(void)
 {
 	char *s;
-	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+	u32 maxcpuclk = CFG_DA850_EVM_MAX_CPU_CLK;
 	u32 rev = 0;
 
 	s = env_get("maxcpuclk");
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index cd021cc8e5..5ffd420fff 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -139,8 +139,8 @@ const struct lpsc_resource lpsc[] = {
 
 const int lpsc_size = ARRAY_SIZE(lpsc);
 
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK	456000000
+#ifndef CFG_DA850_EVM_MAX_CPU_CLK
+#define CFG_DA850_EVM_MAX_CPU_CLK	456000000
 #endif
 
 int board_early_init_f(void)
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 648d77fd21..de224d4d28 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -62,8 +62,8 @@ DECLARE_GLOBAL_DATA_PTR;
  * To get the boot device from 'am33xx_spl_board_init' to
  * 'board_late_init' we therefore use a scratch register from the RTC.
  */
-#define CONFIG_SYS_RTC_SCRATCH0 0x60
-#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
+#define CFG_SYS_RTC_SCRATCH0 0x60
+#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CFG_SYS_RTC_SCRATCH0)
 
 #ifdef CONFIG_SPL_BUILD
 static void save_boot_device(void)
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 8f3fb5fa81..e7e07fff86 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -10,8 +10,8 @@
 /*
  * CADMUS Board System Registers
  */
-#ifndef CONFIG_SYS_CADMUS_BASE_REG
-#define CONFIG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#ifndef CFG_SYS_CADMUS_BASE_REG
+#define CFG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
 #endif
 
 typedef struct cadmus_reg {
@@ -30,7 +30,7 @@ typedef struct cadmus_reg {
 unsigned int
 get_board_version(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	return cadmus->cm_ver;
 }
@@ -39,7 +39,7 @@ get_board_version(void)
 unsigned long
 get_board_sys_clk(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
 
@@ -57,7 +57,7 @@ get_board_sys_clk(void)
 unsigned int
 get_pci_slot(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	/*
 	 * PCI slot in USER bits CSR[6:7] by convention.
@@ -69,7 +69,7 @@ get_pci_slot(void)
 unsigned int
 get_pci_dual(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
 
 	/*
 	 * PCI DUAL in CM_PCI[3]
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 029d06bbf9..b47ce05251 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -28,9 +28,9 @@
 #endif
 
 #if defined(CONFIG_MPC85xx)
-#define CONFIG_DCFG_ADDR	CFG_SYS_MPC85xx_GUTS_ADDR
+#define CFG_DCFG_ADDR	CFG_SYS_MPC85xx_GUTS_ADDR
 #else
-#define CONFIG_DCFG_ADDR	CFG_SYS_FSL_GUTS_ADDR
+#define CFG_DCFG_ADDR	CFG_SYS_FSL_GUTS_ADDR
 #endif
 
 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
@@ -44,7 +44,7 @@ int fsl_check_boot_mode_secure(void)
 {
 	uint32_t val;
 	struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_DCFG_ADDR);
 
 	val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
 	if (val == ITS_MASK)
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index cb9f454972..7096b107e5 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -149,8 +149,8 @@ static int set_px_corepll(unsigned long corepll)
 	return 1;
 }
 
-#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
-#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
+#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CFG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
 #endif
 
 /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
@@ -159,7 +159,7 @@ static int set_px_corepll(unsigned long corepll)
  * or various other PIXIS registers to determine the values for COREPLL,
  * MPXPLL, and SYSCLK.
  *
- * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
  * register that tells the pixis to use the various PIXIS register.
  */
 static void read_from_px_regs(int set)
@@ -167,18 +167,18 @@ static void read_from_px_regs(int set)
 	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
 
 	if (set)
-		tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+		tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE;
 	else
-		tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+		tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE;
 
 	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
 }
 
-/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
  * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
  */
-#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
-#define CONFIG_SYS_PIXIS_VBOOT_ENABLE	0x04
+#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE
+#define CFG_SYS_PIXIS_VBOOT_ENABLE	0x04
 #endif
 
 /* Configure the source of the boot location
@@ -194,14 +194,14 @@ static void read_from_px_regs_altbank(int set)
 	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
 
 	if (set)
-		tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+		tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE;
 	else
-		tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+		tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE;
 
 	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
 }
 
-/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
  * tells the PIXIS what the alternate flash bank is.
  *
  * Note that it's not really a mask.  It contains the actual LBMAP bits that
@@ -209,8 +209,8 @@ static void read_from_px_regs_altbank(int set)
  * primary bank has these bits set to 0, and the alternate bank has these
  * bits set to 1.
  */
-#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
+#ifndef CFG_SYS_PIXIS_VBOOT_MASK
+#define CFG_SYS_PIXIS_VBOOT_MASK	(0x40)
 #endif
 
 /* Tell the PIXIS to boot from the default flash bank
@@ -220,7 +220,7 @@ static void read_from_px_regs_altbank(int set)
  */
 static void clear_altbank(void)
 {
-	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+	clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
 }
 
 /* Tell the PIXIS to boot from the alternate flash bank
@@ -230,7 +230,7 @@ static void clear_altbank(void)
  */
 static void set_altbank(void)
 {
-	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+	setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
 }
 
 /* Reset the board with watchdog disabled.
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 645c56c73d..cd1f83e3d0 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -314,7 +314,7 @@ int board_eth_init(struct bd_info *bis)
 		mdio_mux[i] = EMI_NONE;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -322,7 +322,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index 3cae2a0867..cc95214c4e 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c
@@ -28,7 +28,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -36,7 +36,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */
diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c
index 71c4c21cd4..d1a2bfe188 100644
--- a/board/freescale/ls1046afrwy/eth.c
+++ b/board/freescale/ls1046afrwy/eth.c
@@ -27,7 +27,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 926bd74ddc..bbf8b8c2be 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -285,7 +285,7 @@ int board_eth_init(struct bd_info *bis)
 		mdio_mux[i] = EMI_NONE;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index af70d10773..bbc22a3cdf 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c
@@ -29,7 +29,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -37,7 +37,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 3e12c816ab..c0d05539c5 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -139,14 +139,14 @@ int board_eth_init(struct bd_info *bis)
 	initialize_lane_to_slot();
 
 	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+		(struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR;
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
 	/* Register the real 1G MDIO bus */
 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the real 10G MDIO bus */
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index ed6b36339f..ad78f72f98 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -41,7 +41,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -49,7 +49,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 3906c8381e..5eca9386f6 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -26,7 +26,7 @@ int board_eth_init(struct bd_info *bis)
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
 	/* Register the real 1G MDIO bus */
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 62261f50ea..569b193eab 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -474,7 +474,7 @@ int board_eth_init(struct bd_info *bis)
 		mdio_mux[i] = EMI_NONE;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -482,7 +482,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 241ee5a4a2..2e52543847 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -54,7 +54,7 @@ int board_eth_init(struct bd_info *bis)
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 
 	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR;
 
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
@@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis)
 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
 
 	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+		(struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR;
 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 
 	/* Register the 10G MDIO bus */
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 559192e900..86992829ca 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -58,7 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6	0x09030000
 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7	0x00000C50
 
-#define CONFIG_SMC911X_BASE 0x08000000
+#define CFG_SMC911X_BASE 0x08000000
 
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
@@ -226,7 +226,7 @@ int board_late_init(void)
 
 #ifdef CONFIG_SMC911X
 	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
-			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+			CFG_SMC911X_BASE, GPMC_SIZE_16M);
 #endif
 	return 0;
 }
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index ea090575fb..8e1ae29e22 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -327,7 +327,7 @@ int board_eth_init(struct bd_info *bis)
 	struct eth_device *dev;
 	uchar eth_addr[6];
 
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	rc = smc911x_initialize(0, CFG_SMC911X_BASE);
 
 	if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
 		dev = eth_get_dev_by_index(0);
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index 429f886771..086421d926 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -109,7 +109,7 @@ int dram_init(void)
 }
 
 static struct coldfire_serial_plat mcf5307_serial_plat = {
-	.base = CONFIG_SYS_UART_BASE,
+	.base = CFG_SYS_UART_BASE,
 	.port = 0,
 	.baudrate = CONFIG_BAUDRATE,
 };
diff --git a/board/ti/omap3evm/evm.c b/board/ti/omap3evm/evm.c
index a7f9a7eca1..a4d6a0138d 100644
--- a/board/ti/omap3evm/evm.c
+++ b/board/ti/omap3evm/evm.c
@@ -33,7 +33,7 @@
 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
 
-#define CONFIG_SMC911X_BASE 0x2C000000
+#define CFG_SMC911X_BASE 0x2C000000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,7 +54,7 @@ static void omap3_evm_get_revision(void)
 	unsigned int smsc_id;
 
 	/* Ethernet PHY ID is stored at ID_REV register */
-	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
+	smsc_id = readl(CFG_SMC911X_BASE + 0x50) & 0xFFFF0000;
 	printf("Read back SMSC id 0x%x\n", smsc_id);
 
 	switch (smsc_id) {