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| author | Dalon Westergreen <dalon.westergreen@intel.com> | 2021-03-01 15:04:16 +0300 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2021-03-08 05:59:12 +0300 |
| commit | 9773ebcfbca23c7d6fe1dc202913b005bc23cc89 (patch) | |
| tree | 56352355ea1a5d62c636ec436dd197cdae684386 /board | |
| parent | 8a3244d0baf691db1b59ff99e6815f53d1acafb1 (diff) | |
| download | u-boot-9773ebcfbca23c7d6fe1dc202913b005bc23cc89.tar.xz | |
Makefile: socfpga: Add target to generate hex output for combined spl and dtb
Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel
SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It
combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Diffstat (limited to 'board')
0 files changed, 0 insertions, 0 deletions