Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664

44 files changed, 1604 insertions, 1686 deletions

diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index e416c9ac0d..2ad3dbd56c 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -1,29 +1,47 @@
-if TARGET_ARISTAINETOS
+if TARGET_ARISTAINETOS2
+
+source "board/aristainetos/common/Kconfig"
 
 config SYS_BOARD
 	default "aristainetos"
 
-config SYS_CONFIG_NAME
+config SYS_BOARD_VERSION
+	default 2
+
+endif
+
+if TARGET_ARISTAINETOS2B
+
+source "board/aristainetos/common/Kconfig"
+
+config SYS_BOARD
 	default "aristainetos"
 
+config SYS_BOARD_VERSION
+	default 3
+
 endif
 
-if TARGET_ARISTAINETOS2
+if TARGET_ARISTAINETOS2BCSL
+
+source "board/aristainetos/common/Kconfig"
 
 config SYS_BOARD
 	default "aristainetos"
 
-config SYS_CONFIG_NAME
-	default "aristainetos2"
+config SYS_BOARD_VERSION
+	default 4
 
 endif
 
-if TARGET_ARISTAINETOS2B
+if TARGET_ARISTAINETOS2C
+
+source "board/aristainetos/common/Kconfig"
 
 config SYS_BOARD
 	default "aristainetos"
 
-config SYS_CONFIG_NAME
-	default "aristainetos2b"
+config SYS_BOARD_VERSION
+	default 5
 
 endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index b463f7b176..b4ca7abb9c 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -2,8 +2,35 @@ ARISTAINETOS BOARD
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 F:	board/aristainetos/
-F:	include/configs/aristainetos.h
-F:	configs/aristainetos_defconfig
 F:	include/configs/aristainetos2.h
 F:	configs/aristainetos2_defconfig
 F:	configs/aristainetos2b_defconfig
+F:	configs/aristainetos2bcsl_defconfig
+F:	configs/aristainetos2c_defconfig
+F:	arch/arm/dts/imx6qdl-aristainetos2.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_4.dts
+F:	arch/arm/dts/imx6dl-aristainetos2_4.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2b_4.dts
+F:	arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2b_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2b.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
+F:	arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_4.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
deleted file mode 100644
index de1a018c1f..0000000000
--- a/board/aristainetos/aristainetos-v1.c
+++ /dev/null
@@ -1,278 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <pwm.h>
-
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
-		.gp = IMX_GPIO_NR(3, 17)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart5_pads[] = {
-	MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const gpio_pads[] = {
-	/* LED enable */
-	MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* spi flash WP protect */
-	MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* backlight enable */
-	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED yellow */
-	MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED red */
-	MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED green */
-	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED blue */
-	MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* i2c4 scl */
-	MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* i2c4 sda */
-	MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* spi CS 1 */
-	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const misc_pads[] = {
-	MX6_PAD_GPIO_1__USB_OTG_ID		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* OTG Power enable */
-	MX6_PAD_EIM_D31__GPIO3_IO31		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_KEY_ROW4__GPIO4_IO15		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_GPIO_16__ENET_REF_CLK	| MUX_PAD_CTRL(0x4001b0a8),
-	MX6_PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
-	/* set GPIO_16 as ENET_REF_CLK_OUT */
-	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-}
-
-static iomux_v3_cfg_t const backlight_pads[] = {
-	MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const ecspi4_pads[] = {
-	MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const display_pads[] = {
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
-	MX6_PAD_DI0_PIN4__GPIO4_IO20,
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
-		? (IMX_GPIO_NR(3, 20)) : -1;
-}
-
-static void setup_spi(void)
-{
-	int i;
-
-	imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
-	for (i = 0; i < 3; i++)
-		enable_spi_clk(true, i);
-
-	/* set cs1 to high */
-	gpio_direction_output(ECSPI4_CS1, 1);
-}
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
-}
-
-int board_eth_init(bd_t *bis)
-{
-	struct iomuxc *iomuxc_regs =
-				(struct iomuxc *)IOMUXC_BASE_ADDR;
-	int ret;
-
-	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
-	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
-
-	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
-	if (ret)
-		return ret;
-
-	setup_iomux_enet();
-	return cpu_eth_init(bis);
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
-	imx_iomux_v3_setup_multiple_pads(
-		display_pads,
-		 ARRAY_SIZE(display_pads));
-	imx_iomux_v3_setup_multiple_pads(
-		backlight_pads,
-		 ARRAY_SIZE(backlight_pads));
-
-	/* enable backlight PWM 3 */
-	if (pwm_init(2, 0, 0))
-		goto error;
-	/* duty cycle 500ns, period: 3000ns */
-	if (pwm_config(2, 500, 3000))
-		goto error;
-	if (pwm_enable(2))
-		goto error;
-	return;
-
-error:
-	puts("error init pwm for backlight\n");
-	return;
-}
-
-static void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	int reg;
-
-	enable_ipu_clock();
-
-	reg = readl(&mxc_ccm->cs2cdr);
-	/* select pll 5 clock */
-	reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
-	reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
-	writel(reg, &mxc_ccm->cs2cdr);
-
-	imx_iomux_v3_setup_multiple_pads(backlight_pads,
-					 ARRAY_SIZE(backlight_pads));
-}
-
-static void setup_iomux_gpio(void)
-{
-	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-	setup_iomux_gpio();
-
-	setup_display();
-	return 0;
-}
-
-
-static void setup_i2c4(void)
-{
-	/* i2c4 not used, set it to gpio input */
-	gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
-	gpio_direction_input(IMX_GPIO_NR(1, 7));
-	gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
-	gpio_direction_input(IMX_GPIO_NR(1, 8));
-}
-
-static void setup_board_gpio(void)
-{
-	/* enable LED */
-	gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
-	gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
-
-	gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
-	gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
-	gpio_request(IMX_GPIO_NR(1, 4), "LED red");
-	gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
-	gpio_request(IMX_GPIO_NR(1, 5), "LED green");
-	gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
-	gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
-	gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
-}
-
-static void setup_board_spi(void)
-{
-}
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
deleted file mode 100644
index a12c063e5b..0000000000
--- a/board/aristainetos/aristainetos-v2.c
+++ /dev/null
@@ -1,687 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <init.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <env.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <pwm.h>
-#include <micrel.h>
-#include <spi.h>
-#include <video.h>
-#include <../drivers/video/imx/ipu.h>
-#if defined(CONFIG_VIDEO_BMP_LOGO)
-	#include <bmp_logo.h>
-#endif
-
-#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW |			\
-	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-	/* 4.3 display controller */
-	#define ECSPI1_CS0		IMX_GPIO_NR(4, 9)
-	#define ECSPI4_CS0		IMX_GPIO_NR(3, 29)
-#elif (CONFIG_SYS_BOARD_VERSION == 3)
-	#define ECSPI1_CS0		IMX_GPIO_NR(2, 30)   /* NOR flash */
-	/* 4.3 display controller */
-	#define ECSPI1_CS1		IMX_GPIO_NR(4, 10)
-#endif
-
-#define SOFT_RESET_GPIO		IMX_GPIO_NR(7, 13)
-#define SD2_DRIVER_ENABLE	IMX_GPIO_NR(7, 8)
-
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
-		.gp = IMX_GPIO_NR(1, 5)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-
-struct i2c_pads_info i2c_pad_info4 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
-		.gp = IMX_GPIO_NR(1, 7)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
-		.gp = IMX_GPIO_NR(1, 8)
-	}
-};
-
-iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D19__UART1_CTS_B    | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D20__UART1_RTS_B    | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart3_pads[] = {
-	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const gpio_pads[] = {
-	/* LED enable*/
-	MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED yellow */
-	MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED red */
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-	MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#elif (CONFIG_SYS_BOARD_VERSION == 3)
-	MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#endif
-	/* LED green */
-	MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LED blue */
-	MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* spi flash WP protect */
-	MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* spi CS 0 */
-	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* spi bus #2 SS driver enable */
-	MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* RST_LOC# PHY reset input (has pull-down!)*/
-	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* SD 2 level shifter output enable */
-	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* SD1 card detect input */
-	MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* SD1 write protect input */
-	MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* SD2 card detect input */
-	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* SD2 write protect input */
-	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* Touchscreen IRQ */
-	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const misc_pads[] = {
-	/* USB_OTG_ID = GPIO1_24*/
-	MX6_PAD_ENET_RX_ER__USB_OTG_ID		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* H1 Power enable = GPIO1_0*/
-	MX6_PAD_GPIO_0__USB_H1_PWR		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* OTG Power enable = GPIO4_15*/
-	MX6_PAD_KEY_ROW4__USB_OTG_PWR		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const backlight_pads[] = {
-	/* backlight PWM brightness control */
-	MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* backlight enable */
-	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* LCD power enable */
-	MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-	MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
-#elif (CONFIG_SYS_BOARD_VERSION == 3)
-	MX6_PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#endif
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-iomux_v3_cfg_t const ecspi4_pads[] = {
-	MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_A25__GPIO5_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
-static iomux_v3_cfg_t const display_pads[] = {
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-		return IMX_GPIO_NR(5, 2);
-
-	if (bus == 0 && cs == 0)
-		return IMX_GPIO_NR(4, 9);
-#elif (CONFIG_SYS_BOARD_VERSION == 3)
-		return ECSPI1_CS0;
-
-	if (bus == 0 && cs == 1)
-		return ECSPI1_CS1;
-#endif
-	return -1;
-}
-
-static void setup_spi(void)
-{
-	int i;
-
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-	imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
-#endif
-
-	for (i = 0; i < 4; i++)
-		enable_spi_clk(true, i);
-
-	gpio_direction_output(ECSPI1_CS0, 1);
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-	gpio_direction_output(ECSPI4_CS1, 0);
-	/* set cs0 to high (second device on spi bus #4) */
-	gpio_direction_output(ECSPI4_CS0, 1);
-#elif (CONFIG_SYS_BOARD_VERSION == 3)
-	gpio_direction_output(ECSPI1_CS1, 1);
-#endif
-}
-
-static void setup_iomux_uart(void)
-{
-	switch (CONFIG_MXC_UART_BASE) {
-	case UART1_BASE:
-		imx_iomux_v3_setup_multiple_pads(uart1_pads,
-						 ARRAY_SIZE(uart1_pads));
-		break;
-	case UART2_BASE:
-		imx_iomux_v3_setup_multiple_pads(uart2_pads,
-						 ARRAY_SIZE(uart2_pads));
-		break;
-	case UART3_BASE:
-		imx_iomux_v3_setup_multiple_pads(uart3_pads,
-						 ARRAY_SIZE(uart3_pads));
-		break;
-	case UART4_BASE:
-		imx_iomux_v3_setup_multiple_pads(uart4_pads,
-						 ARRAY_SIZE(uart4_pads));
-		break;
-	}
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	/* control data pad skew - devaddr = 0x02, register = 0x04 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* tx data pad skew - devaddr = 0x02, register = 0x06 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	setup_iomux_enet();
-	return cpu_eth_init(bis);
-}
-
-static int rotate_logo_one(unsigned char *out, unsigned char *in)
-{
-	int   i, j;
-
-	for (i = 0; i < BMP_LOGO_WIDTH; i++)
-		for (j = 0; j < BMP_LOGO_HEIGHT; j++)
-			out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
-			in[i * BMP_LOGO_WIDTH + j];
-	return 0;
-}
-
-/*
- * Rotate the BMP_LOGO (only)
- * Will only work, if the logo is square, as
- * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
- */
-void rotate_logo(int rotations)
-{
-	unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
-	unsigned char *in_logo;
-	int   i, j;
-
-	if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
-		return;
-
-	in_logo = bmp_logo_bitmap;
-
-	/* one 90 degree rotation */
-	if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
-		rotate_logo_one(out_logo, in_logo);
-
-	/* second 90 degree rotation */
-	if (rotations == 2  ||  rotations == 3)
-		rotate_logo_one(in_logo, out_logo);
-
-	/* third 90 degree rotation */
-	if (rotations == 3)
-		rotate_logo_one(out_logo, in_logo);
-
-	/* copy result back to original array */
-	if (rotations == 1  ||  rotations == 3)
-		for (i = 0; i < BMP_LOGO_WIDTH; i++)
-			for (j = 0; j < BMP_LOGO_HEIGHT; j++)
-				in_logo[i * BMP_LOGO_WIDTH + j] =
-				out_logo[i * BMP_LOGO_WIDTH + j];
-}
-
-static void enable_display_power(void)
-{
-	imx_iomux_v3_setup_multiple_pads(backlight_pads,
-					 ARRAY_SIZE(backlight_pads));
-
-	/* backlight enable */
-	gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
-	/* LCD power enable */
-	gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
-
-	/* enable backlight PWM 1 */
-	if (pwm_init(0, 0, 0))
-		goto error;
-	/* duty cycle 500ns, period: 3000ns */
-	if (pwm_config(0, 50000, 300000))
-		goto error;
-	if (pwm_enable(0))
-		goto error;
-	return;
-
-error:
-	puts("error init pwm for backlight\n");
-	return;
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	int reg;
-	s32 timeout = 100000;
-
-	/* set PLL5 clock */
-	reg = readl(&ccm->analog_pll_video);
-	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
-	writel(reg, &ccm->analog_pll_video);
-
-	/* set PLL5 to 232720000Hz */
-	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
-	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
-	writel(reg, &ccm->analog_pll_video);
-
-	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
-	       &ccm->analog_pll_video_num);
-	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
-	       &ccm->analog_pll_video_denom);
-
-	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
-	writel(reg, &ccm->analog_pll_video);
-
-	while (timeout--)
-		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
-			break;
-	if (timeout < 0)
-		printf("Warning: video pll lock timeout!\n");
-
-	reg = readl(&ccm->analog_pll_video);
-	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
-	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
-	writel(reg, &ccm->analog_pll_video);
-
-	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
-	reg = readl(&ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &ccm->cs2cdr);
-
-	reg = readl(&ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &ccm->cscmr2);
-
-	reg = readl(&ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	writel(reg, &ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
-	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
-	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-
-	return;
-}
-
-static void enable_spi_display(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	int reg;
-	s32 timeout = 100000;
-
-#if defined(CONFIG_VIDEO_BMP_LOGO)
-	rotate_logo(3);  /* portrait display in landscape mode */
-#endif
-
-	/*
-	 * set ldb clock to 28341000 Hz calculated through the formula:
-	 * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
-	 * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
-	 * see:
-	 * https://community.freescale.com/thread/308170
-	 */
-	ipu_set_ldb_clock(28341000);
-
-	reg = readl(&ccm->cs2cdr);
-
-	/* select pll 5 clock */
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	writel(reg, &ccm->cs2cdr);
-
-	/* set PLL5 to 197994996Hz */
-	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
-	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
-	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
-	writel(reg, &ccm->analog_pll_video);
-
-	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
-	       &ccm->analog_pll_video_num);
-	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
-	       &ccm->analog_pll_video_denom);
-
-	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
-	writel(reg, &ccm->analog_pll_video);
-
-	while (timeout--)
-		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
-			break;
-	if (timeout < 0)
-		printf("Warning: video pll lock timeout!\n");
-
-	reg = readl(&ccm->analog_pll_video);
-	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
-	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
-	writel(reg, &ccm->analog_pll_video);
-
-	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
-	reg = readl(&ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &ccm->cs2cdr);
-
-	reg = readl(&ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &ccm->cscmr2);
-
-	reg = readl(&ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
-	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
-	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
-	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
-	writel(reg, &ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
-	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
-	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
-	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-
-	imx_iomux_v3_setup_multiple_pads(
-		display_pads,
-		 ARRAY_SIZE(display_pads));
-
-	return;
-}
-static void setup_display(void)
-{
-	enable_ipu_clock();
-	enable_display_power();
-}
-
-static void setup_iomux_gpio(void)
-{
-	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
-}
-
-static void set_gpr_register(void)
-{
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
-	       IOMUXC_GPR1_EXC_MON_SLVE |
-	       (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
-	       IOMUXC_GPR1_ACT_CS0,
-	       &iomuxc_regs->gpr[1]);
-	writel(0x0, &iomuxc_regs->gpr[8]);
-	writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
-	       IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
-	       &iomuxc_regs->gpr[12]);
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-	setup_iomux_gpio();
-
-	gpio_direction_output(SOFT_RESET_GPIO, 1);
-	gpio_direction_output(SD2_DRIVER_ENABLE, 1);
-	setup_display();
-	set_gpr_register();
-	return 0;
-}
-
-static void setup_i2c4(void)
-{
-	setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
-		  &i2c_pad_info4);
-}
-
-static void setup_board_gpio(void)
-{
-	/* enable all LEDs */
-	gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
-	gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
-
-	/* switch off Status LEDs */
-#if (CONFIG_SYS_BOARD_VERSION == 2)
-	gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
-	gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
-	gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
-	gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
-	gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
-	gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
-	gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
-#elif (CONFIG_SYS_BOARD_VERSION == 3)
-	gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
-	gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
-	gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
-	gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
-	gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-	gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
-	gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
-#endif
-}
-
-static void setup_board_spi(void)
-{
-	/* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
-	gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
-}
-
-int board_late_init(void)
-{
-	char *my_bootdelay;
-	char bootmode = 0;
-	char const *panel = env_get("panel");
-
-	/*
-	 * Check the boot-source. If booting from NOR Flash,
-	 * disable bootdelay
-	 */
-	gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
-	gpio_direction_input(IMX_GPIO_NR(7, 6));
-	gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
-	gpio_direction_input(IMX_GPIO_NR(7, 7));
-	gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
-	gpio_direction_input(IMX_GPIO_NR(7, 1));
-	bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
-	bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
-	bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
-
-	if (bootmode == 7) {
-		my_bootdelay = env_get("nor_bootdelay");
-		if (my_bootdelay != NULL)
-			env_set("bootdelay", my_bootdelay);
-		else
-			env_set("bootdelay", "-2");
-	}
-
-	/* if we have the lg panel, we can initialze it now */
-	if (panel)
-		if (!strcmp(panel, displays[1].mode.name))
-			lg4573_spi_startup(CONFIG_LG4573_BUS,
-					   CONFIG_LG4573_CS,
-					   10000000, SPI_MODE_0);
-
-	return 0;
-}
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 9f744b30b3..c79ac1d339 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -17,138 +17,454 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-#include <input.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
-#include <pwm.h>
+#include <bmp_logo.h>
+#include <dm/root.h>
+#include <env.h>
+#include <i2c_eeprom.h>
+#include <i2c.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <lcd.h>
+#include <led.h>
+#include <splash.h>
+#include <video_fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+enum {
+	BOARD_TYPE_4 = 4,
+	BOARD_TYPE_7 = 7,
+};
 
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#define ARI_BT_4 "aristainetos2_4@2"
+#define ARI_BT_7 "aristainetos2_7@1"
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+int board_phy_config(struct phy_device *phydev)
+{
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* tx data pad skew - devaddr = 0x02, register = 0x06 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+static int rotate_logo_one(unsigned char *out, unsigned char *in)
+{
+	int   i, j;
 
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+	for (i = 0; i < BMP_LOGO_WIDTH; i++)
+		for (j = 0; j < BMP_LOGO_HEIGHT; j++)
+			out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
+			in[i * BMP_LOGO_WIDTH + j];
+	return 0;
+}
 
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/*
+ * Rotate the BMP_LOGO (only)
+ * Will only work, if the logo is square, as
+ * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
+ */
+void rotate_logo(int rotations)
+{
+	unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
+	struct bmp_header *header;
+	unsigned char *in_logo;
+	int   i, j;
+
+	if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
+		return;
+
+	header = (struct bmp_header *)bmp_logo_bitmap;
+	in_logo = bmp_logo_bitmap + header->data_offset;
+
+	/* one 90 degree rotation */
+	if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
+		rotate_logo_one(out_logo, in_logo);
+
+	/* second 90 degree rotation */
+	if (rotations == 2  ||  rotations == 3)
+		rotate_logo_one(in_logo, out_logo);
+
+	/* third 90 degree rotation */
+	if (rotations == 3)
+		rotate_logo_one(out_logo, in_logo);
+
+	/* copy result back to original array */
+	if (rotations == 1  ||  rotations == 3)
+		for (i = 0; i < BMP_LOGO_WIDTH; i++)
+			for (j = 0; j < BMP_LOGO_HEIGHT; j++)
+				in_logo[i * BMP_LOGO_WIDTH + j] =
+				out_logo[i * BMP_LOGO_WIDTH + j];
+}
 
-#define DISP_PAD_CTRL	(0x10)
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	s32 timeout = 100000;
+
+	/* set PLL5 clock */
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* set PLL5 to 232720000Hz */
+	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
+	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
+	writel(reg, &ccm->analog_pll_video);
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
+	       &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
+	       &ccm->analog_pll_video_denom);
+
+	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
+	reg = readl(&ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &ccm->cs2cdr);
+
+	reg = readl(&ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &ccm->cscmr2);
+
+	reg = readl(&ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
+	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
 
-#define ECSPI4_CS1		IMX_GPIO_NR(5, 2)
+static void enable_spi_display(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	s32 timeout = 100000;
 
-#if (CONFIG_SYS_BOARD_VERSION == 1)
-#include "./aristainetos-v1.c"
-#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
-#include "./aristainetos-v2.c"
+#if defined(CONFIG_VIDEO_BMP_LOGO)
+	rotate_logo(3);  /* portrait display in landscape mode */
 #endif
 
+	reg = readl(&ccm->cs2cdr);
+
+	/* select pll 5 clock */
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	writel(reg, &ccm->cs2cdr);
+
+	/* set PLL5 to 197994996Hz */
+	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
+	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
+	writel(reg, &ccm->analog_pll_video);
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
+	       &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
+	       &ccm->analog_pll_video_denom);
+
+	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+	writel(reg, &ccm->analog_pll_video);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	reg = readl(&ccm->analog_pll_video);
+	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+	writel(reg, &ccm->analog_pll_video);
+
+	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
+	reg = readl(&ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &ccm->cs2cdr);
+
+	reg = readl(&ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &ccm->cscmr2);
+
+	reg = readl(&ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
+	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
+	reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
+	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
+	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
 
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
+static void setup_display(void)
+{
+	enable_ipu_clock();
+}
 
-iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
+static void set_gpr_register(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
+	       IOMUXC_GPR1_EXC_MON_SLVE |
+	       (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
+	       IOMUXC_GPR1_ACT_CS0,
+	       &iomuxc_regs->gpr[1]);
+	writel(0x0, &iomuxc_regs->gpr[8]);
+	writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
+	       IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
+	       &iomuxc_regs->gpr[12]);
+}
 
-int dram_init(void)
+extern char __bss_start[], __bss_end[];
+int board_early_init_f(void)
 {
-	gd->ram_size = imx_ddr_size();
+	select_ldb_di_clock_source(MXC_PLL5_CLK);
+	set_gpr_register();
+
+	/*
+	 * clear bss here, so we can use spi driver
+	 * before relocation and read Environment
+	 * from spi flash.
+	 */
+	memset(__bss_start, 0x00, __bss_end - __bss_start);
 
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC1_BASE_ADDR},
-	{USDHC2_BASE_ADDR},
-};
+static void setup_one_led(char *label, int state)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = led_get_by_label(label, &dev);
+	if (ret == 0)
+		led_set_state(dev, state);
+}
+
+static void setup_board_gpio(void)
+{
+	setup_one_led("led_ena", LEDST_ON);
+	/* switch off Status LEDs */
+	setup_one_led("led_yellow", LEDST_OFF);
+	setup_one_led("led_red", LEDST_OFF);
+	setup_one_led("led_green", LEDST_OFF);
+	setup_one_led("led_blue", LEDST_OFF);
+}
+
+#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
+		" rescueReason=%d "
 
-int board_mmc_getcd(struct mmc *mmc)
+static void aristainetos_run_rescue_command(int reason)
 {
-	return 1;
+	char rescue_reason_command[80];
+
+	sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
+	run_command(rescue_reason_command, 0);
 }
 
-int board_mmc_init(bd_t *bis)
+static int aristainetos_eeprom(void)
+{
+	struct udevice *dev;
+	int off;
+	int ret;
+	u8 data[0x10];
+	u8 rescue_reason;
+
+	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+	if (off < 0) {
+		printf("%s: No eeprom0 path offset\n", __func__);
+		return off;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
+	if (ret) {
+		printf("%s: Could not find EEPROM\n", __func__);
+		return ret;
+	}
+
+	ret = i2c_set_chip_offset_len(dev, 2);
+	if (ret)
+		return ret;
+
+	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
+	if (ret) {
+		printf("%s: Could not read EEPROM\n", __func__);
+		return ret;
+	}
+
+	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
+		rescue_reason = *(uint8_t *)&data[9];
+		memset(&data[3], 0xff, 7);
+		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
+		printf("\nBooting into Rescue System (EEPROM)\n");
+		aristainetos_run_rescue_command(rescue_reason);
+		run_command("run rescue_load_fit rescueboot", 0);
+	} else if (strncmp((char *)data, "DeF", 3) == 0) {
+		memset(data, 0xff, 3);
+		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
+		printf("\nClear u-boot environment (set back to defaults)\n");
+		run_command("run default_env; saveenv; saveenv", 0);
+	}
+
+	return 0;
+};
+
+static void aristainetos_bootmode_settings(void)
 {
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-#if (CONFIG_SYS_BOARD_VERSION == 2)
+	struct gpio_desc *desc;
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int sbmr1 = readl(&psrc->sbmr1);
+	char *my_bootdelay;
+	char bootmode = 0;
+	int ret;
+
 	/*
-	 * usdhc2 has a levelshifter on the carrier board Rev. DV1,
-	 * that will automatically detect the driving direction.
-	 * During initialisation this isn't working correctly,
-	 * which causes DAT3 to be driven low towards the SD-card.
-	 * This causes a SD-card enetring the SPI-Mode
-	 * and therefore getting inaccessible until next power cycle.
-	 * As workaround we drive the DAT3 line as GPIO and set it high.
-	 * This makes usdhc2 unusable in u-boot, but works for the
-	 * initialisation in Linux
+	 * Check the boot-source. If booting from NOR Flash,
+	 * disable bootdelay
 	 */
-	imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
-			       MUX_PAD_CTRL(NO_PAD_CTRL));
-	gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
-#endif
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	ret = gpio_hog_lookup_name("bootsel0", &desc);
+	if (!ret)
+		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
+	ret = gpio_hog_lookup_name("bootsel1", &desc);
+	if (!ret)
+		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
+	ret = gpio_hog_lookup_name("bootsel2", &desc);
+	if (!ret)
+		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
+
+	if (bootmode == 7) {
+		my_bootdelay = env_get("nor_bootdelay");
+		if (my_bootdelay)
+			env_set("bootdelay", my_bootdelay);
+		else
+			env_set("bootdelay", "-2");
+	}
+
+	if (sbmr1 & 0x40) {
+		env_set("bootmode", "1");
+		printf("SD bootmode jumper set!\n");
+	} else {
+		env_set("bootmode", "0");
+	}
+
+	/* read out some jumper values*/
+	ret = gpio_hog_lookup_name("env_reset", &desc);
+	if (!ret) {
+		if (dm_gpio_get_value(desc)) {
+			printf("\nClear env (set back to defaults)\n");
+			run_command("run default_env; saveenv; saveenv", 0);
+		}
+	}
+	ret = gpio_hog_lookup_name("boot_rescue", &desc);
+	if (!ret) {
+		if (dm_gpio_get_value(desc)) {
+			aristainetos_run_rescue_command(16);
+			run_command("run rescue_xload_boot", 0);
+		}
+	}
 }
-#endif
 
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
+int board_late_init(void)
+{
+	int x, y;
+
+	led_default_state();
+	splash_get_pos(&x, &y);
+	bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
+
+	aristainetos_bootmode_settings();
+
+	/* eeprom work */
+	aristainetos_eeprom();
+
+	/* set board_type */
+	if (gd->board_type == BOARD_TYPE_4)
+		env_set("board_type", ARI_BT_4);
+	else
+		env_set("board_type", ARI_BT_7);
+
+	return 0;
+}
+
+int dram_init(void)
 {
-	return 1;
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
 }
 
 struct display_info_t const displays[] = {
@@ -174,7 +490,10 @@ struct display_info_t const displays[] = {
 			.vmode          = FB_VMODE_NONINTERLACED
 		}
 	}
-#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
+#if ((CONFIG_SYS_BOARD_VERSION == 2) || \
+	(CONFIG_SYS_BOARD_VERSION == 3) || \
+	(CONFIG_SYS_BOARD_VERSION == 4) || \
+	(CONFIG_SYS_BOARD_VERSION == 5))
 	, {
 		.bus	= -1,
 		.addr	= 0,
@@ -202,12 +521,7 @@ struct display_info_t const displays[] = {
 };
 size_t display_count = ARRAY_SIZE(displays);
 
-/* no console on this board */
-int board_cfb_skip(void)
-{
-	return 1;
-}
-
+#if defined(CONFIG_NAND)
 iomux_v3_cfg_t nfc_pads[] = {
 	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -261,6 +575,11 @@ static void setup_gpmi_nand(void)
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 }
+#else
+static void setup_gpmi_nand(void)
+{
+}
+#endif
 
 int board_init(void)
 {
@@ -269,57 +588,54 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	setup_spi();
-
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
-		  &i2c_pad_info1);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
-		  &i2c_pad_info2);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
-		  &i2c_pad_info3);
-	setup_i2c4();
-
-	/* SPI NOR Flash read only */
-	gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
-	gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
-	gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
-
 	setup_board_gpio();
 	setup_gpmi_nand();
-	setup_board_spi();
+	setup_display();
 
 	/* GPIO_1 for USB_OTG_ID */
 	clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
-	imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 	return 0;
 }
 
-int checkboard(void)
+int board_fit_config_name_match(const char *name)
 {
-	printf("Board: %s\n", CONFIG_BOARDNAME);
-	return 0;
+	if (gd->board_type == BOARD_TYPE_4 &&
+	    strchr(name, 0x34))
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_7 &&
+	    strchr(name, 0x37))
+		return 0;
+
+	return -1;
 }
 
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
+static void do_board_detect(void)
 {
 	int ret;
+	char s[30];
 
-	ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
-	if (!ret)
-		gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
-	ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
-	if (!ret)
-		gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
-	return 0;
+	/* default use board type 7 */
+	gd->board_type = BOARD_TYPE_7;
+	if (env_init())
+		return;
+
+	ret = env_get_f("panel", s, sizeof(s));
+	if (ret < 0)
+		return;
+
+	if (!strncmp("lg4573", s, 6))
+		gd->board_type = BOARD_TYPE_4;
 }
 
-int board_ehci_power(int port, int on)
+#ifdef CONFIG_DTB_RESELECT
+int embedded_dtb_select(void)
 {
-	if (port)
-		gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
-	else
-		gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
+	int rescan;
+
+	do_board_detect();
+	fdtdec_resetup(&rescan);
+
 	return 0;
 }
 #endif
diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg
deleted file mode 100644
index fb746782ac..0000000000
--- a/board/aristainetos/aristainetos.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2013 Boundary Devices
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd
- */
-BOOT_FROM      spi
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#include "mt41j128M.cfg"
-#include "clocks.cfg"
diff --git a/board/aristainetos/aristainetos2.cfg b/board/aristainetos/aristainetos2.cfg
index fbbc2e5e6d..965ad64b49 100644
--- a/board/aristainetos/aristainetos2.cfg
+++ b/board/aristainetos/aristainetos2.cfg
@@ -23,6 +23,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg
deleted file mode 100644
index 58976e72b0..0000000000
--- a/board/aristainetos/clocks.cfg
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00c03f3f
-DATA 4, CCM_CCGR1, 0x0030fcff
-DATA 4, CCM_CCGR2, 0x0fffcfc0
-DATA 4, CCM_CCGR3, 0x3ff0300f
-DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0f0000c3
-DATA 4, CCM_CCGR6, 0x000003ff
diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig
new file mode 100644
index 0000000000..e26de5144d
--- /dev/null
+++ b/board/aristainetos/common/Kconfig
@@ -0,0 +1,35 @@
+config SYS_BOARD_VERSION
+	int "select version of aristainetos board"
+	help
+	  version of aristainetos board version
+	  2 version 2
+	  3 version 2b
+	  4 version 2bcsl
+	  5 version 2c
+
+config SYS_I2C_MXC_I2C1
+	default y
+
+config SYS_I2C_MXC_I2C2
+	default y
+
+config SYS_I2C_MXC_I2C3
+	default y
+
+config SYS_I2C_MXC_I2C4
+	default y
+
+config SYS_MALLOC_LEN
+	default 0x4000000
+
+config ENV_SIZE
+	default 0x3000
+
+config ENV_SECT_SIZE
+	default 0x10000
+
+config ENV_OFFSET
+	default 0xd0000
+
+config SYS_CONFIG_NAME
+	default "aristainetos2"
diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg
deleted file mode 100644
index d3ade356e5..0000000000
--- a/board/aristainetos/ddr-setup.cfg
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* DDR IO TYPE */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-/* Clock */
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
-/* Address */
-DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* Control */
-DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-/* Data Strobe */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg
deleted file mode 100644
index bb2684bc37..0000000000
--- a/board/aristainetos/mt41j128M.cfg
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- */
-/* ZQ Calibration */
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
-/*
- * DQS gating, read delay, write delay calibration values
- * based on calibration compare of 0x00ffff00
- */
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
-/* read data bit delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-/* Complete calibration by forced measurment */
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-/* in DDR3, 64-bit mode, only MMDC0 is initiated */
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
-/* MR2 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
-/* MR3 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
-/* MR1 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
-/* MR0 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
-/* final ddr setup */
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
-DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c
index 63a54f59b8..398e4ed720 100644
--- a/board/beckhoff/mx53cx9020/mx53cx9020.c
+++ b/board/beckhoff/mx53cx9020/mx53cx9020.c
@@ -129,16 +129,6 @@ static void setup_gpio_leds(void)
 	gpio_direction_output(GPIO_LED_PWR_G, 0);
 }
 
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
-	/* request VBUS power enable pin, GPIO7_8 */
-	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
-	return 0;
-}
-#endif
-
-
 static int power_init(void)
 {
 	/* nothing to do on CX9020 */
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index b20ca168df..3e185ad82a 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -147,6 +147,11 @@ int board_video_skip(void)
 static inline void cm_fx6_setup_display(void) {}
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+int ipu_displays_init(void)
+{
+	return board_video_skip();
+}
+
 #ifdef CONFIG_DWC_AHSATA
 static int cm_fx6_issd_gpios[] = {
 	/* The order of the GPIOs in the array is important! */
diff --git a/board/ea/mx7ulp_com/Kconfig b/board/ea/mx7ulp_com/Kconfig
new file mode 100644
index 0000000000..90883aced4
--- /dev/null
+++ b/board/ea/mx7ulp_com/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_COM
+
+config SYS_BOARD
+	default "mx7ulp_com"
+
+config SYS_VENDOR
+	default "ea"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_com"
+
+endif
diff --git a/board/ea/mx7ulp_com/MAINTAINERS b/board/ea/mx7ulp_com/MAINTAINERS
new file mode 100644
index 0000000000..3f69511b1a
--- /dev/null
+++ b/board/ea/mx7ulp_com/MAINTAINERS
@@ -0,0 +1,6 @@
+MX7ULPCOM BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/ea/mx7ulp_com/
+F:	include/configs/mx7ulp_com.h
+F:	configs/mx7ulp_com_defconfig
diff --git a/board/ea/mx7ulp_com/Makefile b/board/ea/mx7ulp_com/Makefile
new file mode 100644
index 0000000000..b3b230b172
--- /dev/null
+++ b/board/ea/mx7ulp_com/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_com.o
diff --git a/board/ea/mx7ulp_com/imximage.cfg b/board/ea/mx7ulp_com/imximage.cfg
new file mode 100644
index 0000000000..d298d17c1e
--- /dev/null
+++ b/board/ea/mx7ulp_com/imximage.cfg
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00dc 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000001
+DATA 4   0x403E0514 0x00000014
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+/*
+ * Default PFD0 divide is 27, which generates:
+ * PFD0 Freq = A7 APLL (528MHz) * 18 / 27 = 352MHz
+ *
+ * i.MX7ULP COM board can not run DDR at 352MHz, so
+ * use a divider of 30 (0x1E), which gives:
+ *
+ * PFD0 Freq = A7 APLL (528MHz) * 18 / 30 = 316.8MHz
+ */
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00dc 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0890 0x00400000
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB0848 0x3A3E3838
+DATA 4   0x40AB0850 0x28282C2A
+DATA 4   0x40AB083C 0x20000000
+DATA 4   0x40AB0840 0x00000000
+DATA 4   0x40AB08B8 0x00000800
+DATA 4   0x40AB000C 0x292C40F5
+DATA 4   0x40AB0004 0x00020064
+DATA 4   0x40AB0010 0xB6AD0A83
+DATA 4   0x40AB0014 0x00C70093
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0038 0x00130556
+DATA 4   0x40AB0008 0x12272000
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x06028030
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x06028038
+DATA 4   0x40AB001C 0x01038038
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310003
+DATA 4   0x40AB001C 0x00000000
+#endif
diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c b/board/ea/mx7ulp_com/mx7ulp_com.c
new file mode 100644
index 0000000000..6fc1631bf7
--- /dev/null
+++ b/board/ea/mx7ulp_com/mx7ulp_com.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL		(PAD_CTL_PUS_UP)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
+					 ARRAY_SIZE(lpuart4_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
index e5358b47f3..6472d382c9 100644
--- a/board/engicam/common/board.c
+++ b/board/engicam/common/board.c
@@ -10,6 +10,8 @@
 #include <env.h>
 #include <init.h>
 #include <mmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <watchdog.h>
 
@@ -35,35 +37,102 @@ static void mmc_late_init(void)
 }
 #endif
 
-static void setenv_fdt_file(void)
+enum engicam_boards {
+	IMX6Q_ICORE,
+	IMX6DL_ICORE,
+	IMX6Q_ICORE_MIPI,
+	IMX6DL_ICORE_MIPI,
+	IMX6Q_ICORE_RQS,
+	IMX6DL_ICORE_RQS,
+	IMX6UL_GEAM,
+	IMX6UL_ISIOT_EMMC,
+	IMX6UL_ISIOT_NAND,
+	ENGICAM_BOARDS,
+};
+
+static const char * const board_fdt_file[ENGICAM_BOARDS] = {
+	[IMX6Q_ICORE] = "imx6q-icore.dtb",
+	[IMX6DL_ICORE] = "imx6dl-icore.dtb",
+	[IMX6Q_ICORE_MIPI] = "imx6q-icore-mipi.dtb",
+	[IMX6DL_ICORE_MIPI] = "imx6dl-icore-mipi.dtb",
+	[IMX6Q_ICORE_RQS] = "imx6q-icore-rqs.dtb",
+	[IMX6DL_ICORE_RQS] = "imx6dl-icore-rqs.dtb",
+	[IMX6UL_GEAM] = "imx6ul-geam.dtb",
+	[IMX6UL_ISIOT_EMMC] = "imx6ul-isiot-emmc.dtb",
+	[IMX6UL_ISIOT_NAND] = "imx6ul-isiot-nand.dtb",
+};
+
+static int setenv_fdt_file(int board_detected)
+{
+	if (board_detected < 0 || board_detected >= ENGICAM_BOARDS)
+		return -EINVAL;
+
+	if (!board_fdt_file[board_detected])
+		return -ENODEV;
+
+	env_set("fdt_file", board_fdt_file[board_detected]);
+	return 0;
+}
+
+static enum engicam_boards engicam_board_detect(void)
 {
 	const char *cmp_dtb = CONFIG_DEFAULT_DEVICE_TREE;
 
 	if (!strcmp(cmp_dtb, "imx6q-icore")) {
 		if (is_mx6dq())
-			env_set("fdt_file", "imx6q-icore.dtb");
+			return IMX6Q_ICORE;
 		else if (is_mx6dl() || is_mx6solo())
-			env_set("fdt_file", "imx6dl-icore.dtb");
+			return IMX6DL_ICORE;
 	} else if (!strcmp(cmp_dtb, "imx6q-icore-mipi")) {
 		if (is_mx6dq())
-			env_set("fdt_file", "imx6q-icore-mipi.dtb");
+			return IMX6Q_ICORE_MIPI;
 		else if (is_mx6dl() || is_mx6solo())
-			env_set("fdt_file", "imx6dl-icore-mipi.dtb");
+			return IMX6DL_ICORE_MIPI;
 	} else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) {
 		if (is_mx6dq())
-			env_set("fdt_file", "imx6q-icore-rqs.dtb");
+			return IMX6Q_ICORE_RQS;
 		else if (is_mx6dl() || is_mx6solo())
-			env_set("fdt_file", "imx6dl-icore-rqs.dtb");
+			return IMX6DL_ICORE_RQS;
 	} else if (!strcmp(cmp_dtb, "imx6ul-geam"))
-		env_set("fdt_file", "imx6ul-geam.dtb");
+			return IMX6UL_GEAM;
 	else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))
-		env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
+			return IMX6UL_ISIOT_EMMC;
 	else if (!strcmp(cmp_dtb, "imx6ul-isiot-nand"))
-		env_set("fdt_file", "imx6ul-isiot-nand.dtb");
+			return IMX6UL_ISIOT_NAND;
+
+	return -EINVAL;
+}
+
+static int fixup_enet_clock(enum engicam_boards board_detected)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int clk_internal = 0;
+
+	switch (board_detected) {
+	case IMX6Q_ICORE_MIPI:
+	case IMX6DL_ICORE_MIPI:
+		clk_internal = 1;
+		break;
+	default:
+		break;
+	}
+
+	/* set gpr1[21] to select anatop clock */
+	debug("fixup_enet_clock %d\n", clk_internal);
+	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, clk_internal << 21);
+
+	if (!clk_internal) {
+		/* clock is external */
+		return 0;
+	}
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 
 int board_late_init(void)
 {
+	enum engicam_boards board_detected = IMX6Q_ICORE;
+
 	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
 			IMX6_BMODE_SHIFT) {
 	case IMX6_BMODE_SD:
@@ -88,7 +157,12 @@ int board_late_init(void)
 	else
 		env_set("console", "ttymxc3");
 
-	setenv_fdt_file();
+	board_detected = engicam_board_detect();
+	if (board_detected < 0)
+		hang();
+
+	fixup_enet_clock(board_detected);
+	setenv_fdt_file(board_detected);
 
 #ifdef CONFIG_HW_WATCHDOG
 	hw_watchdog_init();
diff --git a/board/freescale/imx8mm_evk/README b/board/freescale/imx8mm_evk/README
index a885bc5c97..c908c0adc4 100644
--- a/board/freescale/imx8mm_evk/README
+++ b/board/freescale/imx8mm_evk/README
@@ -9,18 +9,18 @@ Quick Start
 
 Get and Build the ARM Trusted firmware
 ======================================
-Note: srctree is U-Boot source directory
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
 Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
 branch: imx_4.19.35_1.0.0
 $ make PLAT=imx8mm bl31
-$ cp build/imx8mm/release/bl31.bin $(srctree)
+$ cp build/imx8mm/release/bl31.bin $(builddir)
 
 Get the ddr and hdmi firmware
 =============================
 $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
 $ chmod +x firmware-imx-8.0.bin
 $ ./firmware-imx-8.0
-$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
 
 Build U-Boot
 ============
diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README
index 4f671b069c..859f852255 100644
--- a/board/freescale/imx8mq_evk/README
+++ b/board/freescale/imx8mq_evk/README
@@ -13,15 +13,15 @@ Note: srctree is U-Boot source directory
 Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
 branch: imx_4.19.35_1.0.0
 $ make PLAT=imx8mq bl31
-$ cp build/imx8mq/release/bl31.bin $(srctree)
+$ cp build/imx8mq/release/bl31.bin $(builddir)
 
 Get the ddr and hdmi firmware
 =============================
 $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
 $ chmod +x firmware-imx-7.9.bin
 $ ./firmware-imx-7.9.bin
-$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
-$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
 
 Build U-Boot
 ============
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 33ae91c307..453f281418 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -145,7 +145,7 @@ int power_init_board(void)
 	u32 switch_num = 6;
 	u32 offset = PFUZE100_SW1CMODE;
 
-	ret = pmic_get("pfuze100", &dev);
+	ret = pmic_get("pfuze100@08", &dev);
 	if (ret == -ENODEV)
 		return 0;
 
diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c
index 227d178e07..0a36b46e9e 100644
--- a/board/freescale/mx6sllevk/mx6sllevk.c
+++ b/board/freescale/mx6sllevk/mx6sllevk.c
@@ -57,7 +57,7 @@ int power_init_board(void)
 	u32 switch_num = 6;
 	u32 offset = PFUZE100_SW1CMODE;
 
-	ret = pmic_get("pfuze100", &dev);
+	ret = pmic_get("pfuze100@08", &dev);
 	if (ret == -ENODEV)
 		return 0;
 
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index f1120d67e3..835eed3316 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -16,7 +16,6 @@
 #include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <miiphy.h>
-#include <netdev.h>
 #include <power/pmic.h>
 #include <power/pfuze3000_pmic.h>
 #include "../common/pfuze.h"
@@ -29,11 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
-
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
 	PAD_CTL_DSE_3P3V_49OHM)
 
@@ -170,30 +164,6 @@ static int setup_lcd(void)
 }
 #endif
 
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
-	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-};
-
-static void setup_iomux_fec(void)
-{
-	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-}
-#endif
-
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -216,37 +186,6 @@ int mmc_map_to_kernel_blk(int dev_no)
 }
 
 #ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-	unsigned int gpio;
-
-	ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
-	if (ret) {
-		printf("GPIO: 'gpio_spi@0_5' not found\n");
-		return -ENODEV;
-	}
-
-	ret = gpio_request(gpio, "fec_rst");
-	if (ret && ret != -EBUSY) {
-		printf("gpio: requesting pin %u failed\n", gpio);
-		return ret;
-	}
-
-	gpio_direction_output(gpio, 0);
-	udelay(500);
-	gpio_direction_output(gpio, 1);
-
-	setup_iomux_fec();
-
-	ret = fecmxc_initialize_multi(bis, 0,
-		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-	if (ret)
-		printf("FEC1 MXC: %s:failed\n", __func__);
-
-	return ret;
-}
-
 static int setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
@@ -260,7 +199,6 @@ static int setup_fec(void)
 	return set_clk_enet(ENET_125MHZ);
 }
 
-
 int board_phy_config(struct phy_device *phydev)
 {
 	/* enable rgmii rxc skew and phy mode select to RGMII copper */
@@ -326,7 +264,7 @@ int power_init_board(void)
 	struct udevice *dev;
 	int ret, dev_id, rev_id;
 
-	ret = pmic_get("pfuze3000", &dev);
+	ret = pmic_get("pfuze3000@08", &dev);
 	if (ret == -ENODEV)
 		return 0;
 	if (ret != 0)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 2f6747b70a..89607cf056 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -32,12 +32,15 @@
 #include <pwm.h>
 #include <version.h>
 #include <stdlib.h>
+#include <dm/root.h>
 #include "../common/ge_common.h"
 #include "../common/vpd_reader.h"
 #include "../../../drivers/net/e1000.h"
+#include <pci.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
-static int confidx = 3;  /* Default to b850v3. */
+static int confidx;  /* Default to generic. */
 static struct vpd_cache vpd;
 
 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
@@ -82,38 +85,6 @@ static iomux_v3_cfg_t const uart4_pads[] = {
 	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	/* AR8033 PHY Reset */
-	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
-	/* Reset AR8033 PHY */
-	gpio_request(IMX_GPIO_NR(1, 28), "fec_rst");
-	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
-	mdelay(1);
-}
-
 static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
@@ -153,16 +124,6 @@ static struct i2c_pads_info i2c_pad_info3 = {
 	}
 };
 
-static iomux_v3_cfg_t const pcie_pads[] = {
-	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_pcie(void)
-{
-	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
-}
-
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
@@ -218,13 +179,6 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 	imx_enable_hdmi_phy();
 }
 
-int board_cfb_skip(void)
-{
-	gpio_direction_output(LVDS_POWER_GP, 1);
-
-	return 0;
-}
-
 static int is_b850v3(void)
 {
 	return confidx == 3;
@@ -461,7 +415,7 @@ static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
 
 static void process_vpd(struct vpd_cache *vpd)
 {
-	int fec_index = -1;
+	int fec_index = 0;
 	int i210_index = -1;
 
 	if (!vpd->is_read) {
@@ -469,41 +423,30 @@ static void process_vpd(struct vpd_cache *vpd)
 		return;
 	}
 
+	if (vpd->has & VPD_HAS_MAC1)
+		eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
+
+	env_set("ethact", "eth0");
+
 	switch (vpd->product_id) {
 	case VPD_PRODUCT_B450:
 		env_set("confidx", "1");
-		i210_index = 0;
-		fec_index = 1;
+		i210_index = 1;
 		break;
 	case VPD_PRODUCT_B650:
 		env_set("confidx", "2");
-		i210_index = 0;
-		fec_index = 1;
+		i210_index = 1;
 		break;
 	case VPD_PRODUCT_B850:
 		env_set("confidx", "3");
-		i210_index = 1;
-		fec_index = 2;
+		i210_index = 2;
 		break;
 	}
 
-	if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
-		eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
-
 	if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
 		eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
 }
 
-int board_eth_init(bd_t *bis)
-{
-	setup_iomux_enet();
-	setup_pcie();
-
-	e1000_initialize(bis);
-
-	return cpu_eth_init(bis);
-}
-
 static iomux_v3_cfg_t const misc_pads[] = {
 	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
@@ -553,8 +496,16 @@ int board_init(void)
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 
 	if (!read_vpd(&vpd, vpd_callback)) {
+		int ret, rescan;
+
 		vpd.is_read = true;
 		set_confidx(&vpd);
+
+		ret = fdtdec_resetup(&rescan);
+		if (!ret && rescan) {
+			dm_uninit();
+			dm_init_and_scan(false);
+		}
 	}
 
 	gpio_request(SUS_S3_OUT, "sus_s3_out");
@@ -657,6 +608,8 @@ int board_late_init(void)
 
 	check_time();
 
+	pci_init();
+
 	return 0;
 }
 
@@ -696,29 +649,51 @@ int checkboard(void)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	char *rtc_status = env_get("rtc_status");
+
 	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
-	                                    strlen(version_string) + 1);
+		    strlen(version_string) + 1);
+
+	fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
+		    strlen(rtc_status) + 1);
 	return 0;
 }
 #endif
 
 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#if CONFIG_IS_ENABLED(DM_VIDEO)
+	int ret;
+	struct udevice *dev;
+
 #ifdef CONFIG_VIDEO_IPUV3
-	/* We need at least 200ms between power on and backlight on
-	 * as per specifications from CHI MEI */
-	mdelay(250);
+	if (!is_b850v3()) {
+		gpio_direction_output(LVDS_POWER_GP, 1);
 
-	/* enable backlight PWM 1 */
-	pwm_init(0, 0, 0);
+		/* We need at least 200ms between power on and backlight on
+		 * as per specifications from CHI MEI
+		 */
+		mdelay(250);
 
-	/* duty cycle 5000000ns, period: 5000000ns */
-	pwm_config(0, 5000000, 5000000);
+		/* enable backlight PWM 1 */
+		pwm_init(0, 0, 0);
 
-	/* Backlight Power */
-	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+		/* duty cycle 5000000ns, period: 5000000ns */
+		pwm_config(0, 5000000, 5000000);
+
+		/* Backlight Power */
+		gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+
+		pwm_enable(0);
+	}
+#endif
 
-	pwm_enable(0);
+	/* Probe, to find a video device to be used to show a message on
+	 * the vidconsole.
+	 */
+	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
+	if (ret)
+		return ret;
 #endif
 
 	return 0;
@@ -729,3 +704,26 @@ U_BOOT_CMD(
        "enable Bx50 backlight",
        ""
 );
+
+int board_fit_config_name_match(const char *name)
+{
+	if (!vpd.is_read)
+		return strcmp(name, "imx6q-bx50v3");
+
+	switch (vpd.product_id) {
+	case VPD_PRODUCT_B450:
+		return strcmp(name, "imx6q-b450v3");
+	case VPD_PRODUCT_B650:
+		return strcmp(name, "imx6q-b650v3");
+	case VPD_PRODUCT_B850:
+		return strcmp(name, "imx6q-b850v3");
+	default:
+		return -1;
+	}
+}
+
+int embedded_dtb_select(void)
+{
+	vpd.is_read = false;
+	return fdtdec_setup();
+}
diff --git a/board/ge/common/ge_common.c b/board/ge/common/ge_common.c
index 501c8b2daf..d7e21deca7 100644
--- a/board/ge/common/ge_common.c
+++ b/board/ge/common/ge_common.c
@@ -17,8 +17,10 @@ void check_time(void)
 	unsigned int current_i2c_bus = i2c_get_bus_num();
 
 	ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
-	if (ret < 0)
+	if (ret < 0) {
+		env_set("rtc_status", "FAIL");
 		return;
+	}
 
 	rtc_init();
 
@@ -28,10 +30,7 @@ void check_time(void)
 			break;
 	}
 
-	if (ret < 0)
-		env_set("rtc_status", "RTC_ERROR");
-
-	if (tm.tm_year > 2037) {
+	if (!ret && tm.tm_year > 2037) {
 		tm.tm_sec  = 0;
 		tm.tm_min  = 0;
 		tm.tm_hour = 0;
@@ -46,10 +45,17 @@ void check_time(void)
 				break;
 		}
 
-		if (ret < 0)
-			env_set("rtc_status", "RTC_ERROR");
+		if (ret >= 0)
+			ret = 2038;
 	}
 
+	if (ret < 0)
+		env_set("rtc_status", "FAIL");
+	else if (ret == 2038)
+		env_set("rtc_status", "2038");
+	else
+		env_set("rtc_status", "OK");
+
 	i2c_set_bus_num(current_i2c_bus);
 }
 
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index 51b5d8996d..105edd24cb 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -297,7 +297,6 @@ int board_late_init(void)
 		return res;
 
 	print_cpuinfo();
-	hw_watchdog_init();
 
 	check_time();
 
@@ -314,8 +313,13 @@ int checkboard(void)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	char *rtc_status = env_get("rtc_status");
+
 	fdt_setprop(blob, 0, "ge,boot-ver", version_string,
-	                                    strlen(version_string) + 1);
+		    strlen(version_string) + 1);
+
+	fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
+		    strlen(rtc_status) + 1);
 	return 0;
 }
 #endif
diff --git a/board/liebherr/xea/Kconfig b/board/liebherr/xea/Kconfig
new file mode 100644
index 0000000000..5428de4646
--- /dev/null
+++ b/board/liebherr/xea/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_XEA
+
+config SYS_BOARD
+	default "xea"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "xea"
+
+config ENV_SIZE
+	default 0x2000
+
+config ENV_SECT_SIZE
+	default 0x10000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x80000 if ENV_IS_IN_SPI_FLASH
+
+endif
diff --git a/board/liebherr/xea/MAINTAINERS b/board/liebherr/xea/MAINTAINERS
new file mode 100644
index 0000000000..623184d0f8
--- /dev/null
+++ b/board/liebherr/xea/MAINTAINERS
@@ -0,0 +1,6 @@
+XEA BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/xea/
+F:	include/configs/xea.h
+F:	configs/imx28_xea_defconfig
diff --git a/board/liebherr/xea/Makefile b/board/liebherr/xea/Makefile
new file mode 100644
index 0000000000..abf500857f
--- /dev/null
+++ b/board/liebherr/xea/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2019
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= xea.o
+
+ifdef	CONFIG_SPL_BUILD
+obj-y	+= spl_xea.o
+endif
diff --git a/board/liebherr/xea/README b/board/liebherr/xea/README
new file mode 100644
index 0000000000..3e55d3ea43
--- /dev/null
+++ b/board/liebherr/xea/README
@@ -0,0 +1,63 @@
+Building SPL/U-Boot for xea board
+=================================
+
+Setup environment, configure and build, e.g. by:
+
+ $ make imx28_xea_defconfig
+ $ make -j4 u-boot.sb u-boot.img
+
+Now you should see u-boot.sb and u-boot.img files in the build directory.
+
+
+Booting
+=======
+
+The boot ROM loads SPL from SPI NOR flash into SRAM.  SPL configures
+DRAM and loads either a Linux kernel (falcon mode) or, if the rescue
+pin is asserted, the main U-Boot.  Both kernel and U-Boot reside in
+eMMC boot partition 0.  For redundancy, a copy of U-Boot is also
+stored in SPI flash.  If a valid kernel image is not found, U-Boot is
+loaded from eMMC or, if this fails, SPI flash.
+
+Boot area layout
+----------------
+
+SPI NOR
+Offset          Function        File
+------------------------------------------
+0x00000000      SPL             u-boot.sb
+0x00010000      U-Boot          u-boot.img
+0x00080000      Environment
+
+eMMC
+Offset          Function        File
+------------------------------------------
+0x00000000      U-Boot          u-boot.img
+0x00080000      Devicetree      imx28-bttc.dtb
+0x00100000      Kernel          uImage
+
+
+Falcon mode
+===========
+
+In falcon mode, the default, SPL loads the kernel and devicetree
+directly.  For this to work, the stored devicetree must include
+correct "memory" and "chosen" nodes as these are not updated by SPL
+before booting the kernel.
+
+
+Updating from U-Boot
+====================
+
+The default U-Boot environment includes command sequences to update
+SPL, U-Boot, and kernel over TFTP.  These are as follows:
+
+- update_spl: writes u-boot.sb to SPI NOR
+- update_uboot: writes u-boot.img to eMMC and SPI NOR
+- update_kernel: writes kernel and devicetree to eMMC
+
+They can be invoked at the U-Boot prompt using the "run" command,
+e.g. "run update_spl" to update the SPL.
+
+These update commands download the above-named files from the
+${hostname} directory on the server provided by DHCP.
diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c
new file mode 100644
index 0000000000..d88b75bb3a
--- /dev/null
+++ b/board/liebherr/xea/spl_xea.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DENX M28 Boot setup
+ *
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_BOOT	(MXS_PAD_3V3 | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* AUART0 IRDA */
+	MX28_PAD_AUART0_RX__AUART0_RX,
+	MX28_PAD_AUART0_TX__AUART0_TX,
+
+	/* AUART 4 RS422 */
+	MX28_PAD_AUART0_CTS__AUART4_RX,
+	MX28_PAD_AUART0_RTS__AUART4_TX,
+
+	/* USB0 */
+	MX28_PAD_AUART1_CTS__USB0_OVERCURRENT,
+	MX28_PAD_AUART1_RTS__USB0_ID,
+	MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */
+
+	/* USB1 */
+	MX28_PAD_PWM2__USB1_OVERCURRENT,
+
+	/* eMMC */
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */
+	MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+
+	/* DIG Keys */
+	MX28_PAD_GPMI_D00__GPIO_0_0,
+	MX28_PAD_GPMI_D01__GPIO_0_1,
+	MX28_PAD_GPMI_D02__GPIO_0_2,
+	MX28_PAD_GPMI_D03__GPIO_0_3,
+	MX28_PAD_GPMI_D04__GPIO_0_4,
+	MX28_PAD_GPMI_D05__GPIO_0_5,
+	MX28_PAD_GPMI_D06__GPIO_0_6,
+	MX28_PAD_GPMI_D07__GPIO_0_7,
+
+	/* ADR_0-2 */
+	MX28_PAD_GPMI_CE1N__GPIO_0_17,
+	MX28_PAD_GPMI_CE2N__GPIO_0_18,
+	MX28_PAD_GPMI_CE3N__GPIO_0_19,
+
+	/* Read Keys */
+	MX28_PAD_GPMI_RDY0__GPIO_0_20,
+
+	/* LATCH_EN */
+	MX28_PAD_GPMI_RDY1__GPIO_0_21,
+
+	/* Power off */
+	MX28_PAD_GPMI_RDN__GPIO_0_24,
+
+	/* I2C1 Touch */
+	MX28_PAD_AUART2_CTS__GPIO_3_10,
+	MX28_PAD_AUART2_RTS__GPIO_3_11,
+	MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */
+
+	/* TIVA */
+	MX28_PAD_AUART1_RX__SSP2_CARD_DETECT,
+	MX28_PAD_SSP2_MISO__SSP2_D0,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD,
+	MX28_PAD_SSP2_SCK__SSP2_SCK,
+	MX28_PAD_SSP2_SS0__SSP2_D3,
+	MX28_PAD_SSP2_SS1__GPIO_2_20,
+	MX28_PAD_SSP2_SS2__GPIO_2_21,
+
+	/* SPI3 NOR-Flash */
+	MX28_PAD_AUART1_TX__SSP3_CARD_DETECT,
+	MX28_PAD_AUART2_RX__SSP3_D1,
+	MX28_PAD_AUART2_TX__SSP3_D2,
+	MX28_PAD_SSP3_MISO__SSP3_D0,
+	MX28_PAD_SSP3_MOSI__SSP3_CMD,
+	MX28_PAD_SSP3_SCK__SSP3_SCK,
+	MX28_PAD_SSP3_SS0__SSP3_D3,
+
+	/* NOR-Flash CMD */
+	MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */
+	MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */
+
+	/* I2C0 Codec */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* I2S Codec */
+	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK,
+	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK,
+	MX28_PAD_SAIF0_MCLK__SAIF0_MCLK,
+	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0,
+	MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0,
+
+	/* PWR-Hold */
+	MX28_PAD_SPDIF__GPIO_3_27,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* Uart3 Bluetooth-Interface */
+	MX28_PAD_AUART3_CTS__AUART3_CTS,
+	MX28_PAD_AUART3_RTS__AUART3_RTS,
+	MX28_PAD_AUART3_RX__AUART3_RX,
+	MX28_PAD_AUART3_TX__AUART3_TX,
+
+	/* framebuffer */
+	MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+
+	/* DUART RS232 */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* FEC Ethernet */
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */
+
+	/* TIVA boot control */
+	MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
+	MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
+};
+
+u32 mxs_dram_vals[] = {
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010101, 0x01010101,
+	0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+	0x00000100, 0x00000100, 0x00000000, 0x00000002,
+	0x01010000, 0x07080403, 0x07005303, 0x0b0000c8,
+	0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322,
+	0x02040203, 0x00c8002b, 0x00000000, 0x00000000,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000612, 0x01000102,
+	0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+	0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
+	0x07400300, 0x07400300, 0x07400300, 0x00000005,
+	0x00000000, 0x00000000, 0x01000000, 0x00000000,
+	0x00000001, 0x000f1133, 0x00000000, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00030404,
+	0x00000002, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x01010000,
+	0x01000000, 0x03030000, 0x00010303, 0x01020202,
+	0x00000000, 0x02040101, 0x21002103, 0x00061200,
+	0x06120612, 0x00000642, 0x00000000, 0x00000004,
+	0x00000000, 0x00000080, 0x00000000, 0x00000000,
+	0x00000000, 0xffffffff
+};
+
+void lowlevel_init(void)
+{
+	struct mxs_pinctrl_regs *pinctrl_regs =
+		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+	/* Set EMI drive strength */
+	writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
+	writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+	mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c
new file mode 100644
index 0000000000..1d47f67a7f
--- /dev/null
+++ b/board/liebherr/xea/xea.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * XEA iMX28 board
+ *
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2018 DENX Software Engineering
+ * Måns Rullgård, DENX Software Engineering, mans@mansr.com
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+#include <usb.h>
+#include <serial.h>
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+
+static void init_clocks(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+	/* SSP3 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong arg)
+{
+	init_clocks();
+	preloader_console_init();
+}
+
+static int boot_tiva0, boot_tiva1;
+
+/* Check if TIVAs request booting via U-Boot proper */
+void spl_board_init(void)
+{
+	struct gpio_desc btiva0, btiva1;
+	int ret;
+
+	ret = dm_gpio_lookup_name("GPIO0_23", &btiva0);
+	if (ret)
+		printf("Cannot get GPIO0_23\n");
+
+	ret = dm_gpio_lookup_name("GPIO0_25", &btiva1);
+	if (ret)
+		printf("Cannot get GPIO0_25\n");
+
+	ret = dm_gpio_request(&btiva0, "boot-tiva0");
+	if (ret)
+		printf("Cannot request GPIO0_23\n");
+
+	ret = dm_gpio_request(&btiva1, "boot-tiva1");
+	if (ret)
+		printf("Cannot request GPIO0_25\n");
+
+	dm_gpio_set_dir_flags(&btiva0, GPIOD_IS_IN);
+	dm_gpio_set_dir_flags(&btiva1, GPIOD_IS_IN);
+
+	udelay(1000);
+
+	boot_tiva0 = dm_gpio_get_value(&btiva0);
+	boot_tiva1 = dm_gpio_get_value(&btiva1);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+	spl_boot_list[1] = BOOT_DEVICE_SPI;
+}
+
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	debug("%s: btiva0: %d btiva1: %d\n", __func__, boot_tiva0, boot_tiva1);
+	return !boot_tiva0 || !boot_tiva1;
+}
+#else
+
+int board_early_init_f(void)
+{
+	init_clocks();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct gpio_desc phy_rst;
+	int ret;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	cpu_eth_init(NULL);
+
+	/* PHY INT#/PWDN# */
+	ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst);
+	if (ret) {
+		printf("Cannot get GPIO4_13\n");
+		return ret;
+	}
+
+	ret = dm_gpio_request(&phy_rst, "phy-rst");
+	if (ret) {
+		printf("Cannot request GPIO4_13\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN);
+	udelay(1000);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+#endif	/* CONFIG_SPL_BUILD */
diff --git a/board/phytec/pcl063/MAINTAINERS b/board/phytec/pcl063/MAINTAINERS
index 710b9680d4..02be541cc0 100644
--- a/board/phytec/pcl063/MAINTAINERS
+++ b/board/phytec/pcl063/MAINTAINERS
@@ -2,10 +2,14 @@ PCL063 BOARD
 M:	Martyn Welch <martyn.welch@collabora.com>
 M:	Parthiban Nallathambi <parthitce@gmail.com>
 S:	Maintained
-F:	arch/arm/dts/imx6ul-pcl063.dtsi
-F:	arch/arm/dts/imx6ul-phycore-segin.dts
-F:	arch/arm/dts/imx6ull-phycore-segin.dts
-F:	arch/arm/dts/pcl063-common.dtsi
+F:	arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+F:	arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
+F:	arch/arm/dts/imx6ul-phytec-segin.dtsi
+F:	arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+F:	arch/arm/dts/imx6ull-phytec-phycore-som.dtsi
+F:	arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi
+F:	arch/arm/dts/imx6ull-phytec-segin.dtsi
+F:	arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
 F:	arch/arm/dts/imx6ull-u-boot.dtsi
 F:	board/phytec/pcl063/
 F:	configs/phycore_pcl063_defconfig
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index d6e0c83e0d..6a96f9ecdb 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -66,6 +66,8 @@ enum board_type {
 	UNKNOWN         = 0x03,
 };
 
+static struct gpio_desc board_detect_desc[5];
+
 #define MEM_STRIDE 0x4000000
 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
 {
@@ -155,10 +157,6 @@ static iomux_v3_cfg_t const som_rev_detect[] = {
 	IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usb_pads[] = {
-	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
 static void setup_iomux_uart(void)
 {
 	SETUP_IOMUX_PADS(uart1_pads);
@@ -176,7 +174,7 @@ static struct fsl_esdhc_cfg emmc_cfg = {
 
 int board_mmc_get_env_dev(int devno)
 {
-	return devno - 1;
+	return devno;
 }
 
 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
@@ -198,27 +196,6 @@ int board_mmc_getcd(struct mmc *mmc)
 	return ret;
 }
 
-static int mmc_init_main(bd_t *bis)
-{
-	int ret;
-
-	/*
-	 * Following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    Carrier board MicroSD
-	 * mmc1                    SOM eMMC
-	 */
-	SETUP_IOMUX_PADS(usdhc2_pads);
-	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-	ret = fsl_esdhc_initialize(bis, &usdhc_cfg);
-	if (ret)
-		return ret;
-
-	SETUP_IOMUX_PADS(usdhc3_pads);
-	emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	return fsl_esdhc_initialize(bis, &emmc_cfg);
-}
-
 static int mmc_init_spl(bd_t *bis)
 {
 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
@@ -252,7 +229,7 @@ int board_mmc_init(bd_t *bis)
 	if (IS_ENABLED(CONFIG_SPL_BUILD))
 		return mmc_init_spl(bis);
 
-	return mmc_init_main(bis);
+	return 0;
 }
 
 static iomux_v3_cfg_t const enet_pads[] = {
@@ -284,12 +261,29 @@ static iomux_v3_cfg_t const enet_pads[] = {
 
 static void setup_iomux_enet(void)
 {
+	struct gpio_desc desc;
+	int ret;
+
 	SETUP_IOMUX_PADS(enet_pads);
 
+	ret = dm_gpio_lookup_name("GPIO4_15", &desc);
+	if (ret) {
+		printf("%s: phy reset lookup failed\n", __func__);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "phy-reset");
+	if (ret) {
+		printf("%s: phy reset request failed\n", __func__);
+		return;
+	}
+
 	gpio_direction_output(ETH_PHY_RESET, 0);
 	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
 	udelay(100);
+
+	gpio_free_list_nodev(&desc, 1);
 }
 
 int board_phy_config(struct phy_device *phydev)
@@ -434,21 +428,6 @@ static int setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
-#ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
-{
-	SETUP_IOMUX_PADS(usb_pads);
-}
-
-int board_ehci_hcd_init(int port)
-{
-	if (port == 1)
-		gpio_direction_output(USB_H1_VBUS, 1);
-
-	return 0;
-}
-#endif
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -456,10 +435,6 @@ int board_early_init_f(void)
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-	setup_usb();
-#endif
 	return 0;
 }
 
@@ -477,6 +452,29 @@ int board_init(void)
 	return ret;
 }
 
+static int request_detect_gpios(void)
+{
+	int node;
+	int ret;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
+		"solidrun,hummingboard-detect");
+	if (node < 0)
+		return -ENODEV;
+
+	ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+		"detect-gpios", board_detect_desc,
+		ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
+
+	return ret;
+}
+
+static int free_detect_gpios(void)
+{
+	return gpio_free_list_nodev(board_detect_desc,
+		ARRAY_SIZE(board_detect_desc));
+}
+
 static enum board_type board_type(void)
 {
 	int val1, val2, val3;
@@ -532,7 +530,7 @@ static bool is_rev_15_som(void)
 static bool has_emmc(void)
 {
 	struct mmc *mmc;
-	mmc = find_mmc_device(1);
+	mmc = find_mmc_device(2);
 	if (!mmc)
 		return 0;
 	return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
@@ -540,6 +538,8 @@ static bool has_emmc(void)
 
 int checkboard(void)
 {
+	request_detect_gpios();
+
 	switch (board_type()) {
 	case CUBOXI:
 		puts("Board: MX6 Cubox-i");
@@ -561,13 +561,22 @@ int checkboard(void)
 	else
 		puts("\n");
 
+	free_detect_gpios();
 out:
 	return 0;
 }
 
+/* Override the default implementation, DT model is not accurate */
+int show_board_info(void)
+{
+	return checkboard();
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	request_detect_gpios();
+
 	switch (board_type()) {
 	case CUBOXI:
 		env_set("board_name", "CUBOXI");
@@ -594,11 +603,27 @@ int board_late_init(void)
 	if (has_emmc())
 		env_set("has_emmc", "yes");
 
+	free_detect_gpios();
 #endif
 
 	return 0;
 }
 
+/*
+ * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
+ * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
+ * all Hummingboard/Cubox-i platforms.
+ */
+int board_fit_config_name_match(const char *name)
+{
+	char tmp_name[36];
+
+	snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
+			is_mx6dq() ? "imx6q" : "imx6dl");
+
+	return strcmp(name, tmp_name);
+}
+
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
index 7efe816a78..4a2707e771 100644
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -1,5 +1,5 @@
 Apalis iMX6
-M:	Max Krummenacher <max.krummenacher@toradex.com>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:      https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index d4d6eed11a..d569782a19 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -177,22 +177,6 @@ iomux_v3_cfg_t const enet_pads[] = {
 #	define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 };
 
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static int reset_enet_phy(struct mii_dev *bus)
-{
-	/* Reset KSZ9031 PHY */
-	gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
-	gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
-	mdelay(10);
-	gpio_set_value(GPIO_ENET_PHY_RESET, 1);
-
-	return 0;
-}
-
 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 iomux_v3_cfg_t const gpio_pads[] = {
 	/* Apalis GPIO1 - GPIO8 */
@@ -367,41 +351,6 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	uint32_t base = IMX_FEC_BASE;
-	struct mii_dev *bus = NULL;
-	struct phy_device *phydev = NULL;
-	int ret;
-
-	setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(base, -1);
-	if (!bus)
-		return 0;
-
-	bus->reset = reset_enet_phy;
-	/* scan PHY 4,5,6,7 */
-	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
-	if (!phydev) {
-		free(bus);
-		puts("no PHY found\n");
-		return 0;
-	}
-
-	printf("using PHY at %d\n", phydev->addr);
-	ret = fec_probe(bis, -1, base, bus, phydev);
-	if (ret) {
-		printf("FEC MXC: %s:failed\n", __func__);
-		free(phydev);
-		free(bus);
-	}
-#endif /* CONFIG_FEC_MXC */
-
-	return 0;
-}
-
 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 	/*
 	 * the bootrom sets the iomux to vselect, potentially connecting
diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS
index c8199fa60a..4107d29876 100644
--- a/board/toradex/colibri-imx6ull/MAINTAINERS
+++ b/board/toradex/colibri-imx6ull/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri iMX6ULL
-M:	Stefan Agner <stefan.agner@toradex.com>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
index e25c07306c..76f9446bba 100644
--- a/board/toradex/colibri_imx6/MAINTAINERS
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri iMX6
-M:	Max Krummenacher <max.krummenacher@toradex.com>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:      https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index a5cd8587da..7db9d25544 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -51,9 +51,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
 #define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_SRE_SLOW)
@@ -112,24 +109,6 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
 };
 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 
-iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 iomux_v3_cfg_t const gpio_pads[] = {
 	/* ADDRESS[17:18] [25] used as GPIO */
@@ -371,12 +350,8 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
+int setup_fec(void)
 {
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	uint32_t base = IMX_FEC_BASE;
-	struct mii_dev *bus = NULL;
-	struct phy_device *phydev = NULL;
 	int ret;
 
 	/* provide the PHY clock from the i.MX 6 */
@@ -384,34 +359,6 @@ int board_eth_init(bd_t *bis)
 	if (ret)
 		return ret;
 
-	/* set gpr1[ENET_CLK_SEL] */
-	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
-	setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(base, -1);
-	if (!bus)
-		return 0;
-
-	/* scan PHY 1..7 */
-	phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
-	if (!phydev) {
-		free(bus);
-		puts("no PHY found\n");
-		return 0;
-	}
-
-	phy_reset(phydev);
-	printf("using PHY at %d\n", phydev->addr);
-	ret = fec_probe(bis, -1, base, bus, phydev);
-	if (ret) {
-		printf("FEC MXC: %s:failed\n", __func__);
-		free(phydev);
-		free(bus);
-	}
-#endif /* CONFIG_FEC_MXC */
-
 	return 0;
 }
 
@@ -633,7 +580,9 @@ int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
+#if defined(CONFIG_FEC_MXC)
+	setup_fec();
+#endif
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
index cd0f9c9b2d..178dece797 100644
--- a/board/toradex/colibri_imx7/MAINTAINERS
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri iMX7
-M:	Stefan Agner <stefan.agner@toradex.com>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index b0914a9ead..77197e0fbb 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -159,50 +159,12 @@ void board_preboot_os(void)
 	gpio_direction_output(GPIO_BL_ON, 0);
 }
 
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
-#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
-	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
-#else
-	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-#endif
-	MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
-	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-}
-#endif
-
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
 #ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-
-	setup_iomux_fec();
-
-	ret = fecmxc_initialize_multi(bis, 0,
-		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-	if (ret)
-		printf("FEC1 MXC: %s:failed\n", __func__);
-
-	return ret;
-}
-
 static int setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
@@ -226,12 +188,6 @@ static int setup_fec(void)
 	return set_clk_enet(ENET_50MHZ);
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-	return 0;
-}
 #endif
 
 int board_early_init_f(void)
diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS
index 73b8e5d099..00c03c89b8 100644
--- a/board/toradex/colibri_t30/MAINTAINERS
+++ b/board/toradex/colibri_t30/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri T30
-M:	Stefan Agner <stefan.agner@toradex.com>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 S:	Maintained
 F:	board/toradex/colibri_t30/
 F:	include/configs/colibri_t30.h
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
index 66b2150986..f94cc0fbe2 100644
--- a/board/toradex/colibri_vf/MAINTAINERS
+++ b/board/toradex/colibri_vf/MAINTAINERS
@@ -1,5 +1,5 @@
 Colibri VFxx
-M:	Stefan Agner <stefan.agner@toradex.com>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 W:	http://developer.toradex.com/software/linux/linux-software
 W:	https://www.toradex.com/community
 S:	Maintained