diff options
| author | Tom Rini <trini@konsulko.com> | 2023-07-14 03:38:24 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-07-14 03:38:24 +0300 |
| commit | f6da5e927320acd2131d0bb802103aaf34b67925 (patch) | |
| tree | 660d03cc091f494f63fcec24d9e6a489c3e6291c /board | |
| parent | bf5152d0108683bbaabf9d7a7988f61649fc33f4 (diff) | |
| parent | cdbef023e2538da12b3ca4a2b8a5b7bd1c3ada02 (diff) | |
| download | u-boot-f6da5e927320acd2131d0bb802103aaf34b67925.tar.xz | |
Merge tag 'u-boot-imx-20230713' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20230713
-------------------
Merge for 2023.10.
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
Diffstat (limited to 'board')
35 files changed, 1780 insertions, 872 deletions
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c index 7f2e972425..f36caece7d 100644 --- a/board/advantech/imx8qm_dmsse20_a1/spl.c +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -111,7 +111,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); @@ -120,10 +120,10 @@ int board_mmc_init(struct bd_info *bis) break; case 1: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index b602437c35..922bb0b7d4 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -112,7 +112,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); @@ -121,10 +121,10 @@ int board_mmc_init(struct bd_info *bis) break; case 1: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); - if (ret != SC_ERR_NONE) + if (ret) return ret; imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); diff --git a/board/beacon/imx8mm/MAINTAINERS b/board/beacon/imx8mm/MAINTAINERS index e887db20a2..d48ba8605b 100644 --- a/board/beacon/imx8mm/MAINTAINERS +++ b/board/beacon/imx8mm/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/beacon/imx8mm/ F: include/configs/imx8mm_beacon.h F: configs/imx8mm_beacon_defconfig +F: doc/board/beacon/ diff --git a/board/beacon/imx8mm/README b/board/beacon/imx8mm/README deleted file mode 100644 index 32b24bc03e..0000000000 --- a/board/beacon/imx8mm/README +++ /dev/null @@ -1,37 +0,0 @@ -U-Boot for the Beacon EmbeddedWorks Devkit - -Quick Start -=========== -- Build the ARM Trusted firmware binary -- Get ddr firmware -- Build U-Boot -- Boot - -Get and Build the ARM Trusted firmware -====================================== -Note: $(srctree) is U-Boot source directory - -$ git clone https://github.com/nxp-imx/imx-atf -$ git lf-5.10.72-2.2.0 -$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu- -$ cp build/imx8mm/release/bl31.bin $(srctree) - -Get the DDR firmware -==================== -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin -$ chmod +x firmware-imx-8.9.bin -$ ./firmware-imx-8.9 -$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree) - -Build U-Boot -============ -$ make imx8mm_beacon_defconfig -$ make CROSS_COMPILE=aarch64-linux-gnu- - -Burn U-Boot to microSD Card -=========================== -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 - -Boot -==== -Set Boot switch to SD boot diff --git a/board/beacon/imx8mm/imx8mm_beacon.env b/board/beacon/imx8mm/imx8mm_beacon.env new file mode 100644 index 0000000000..00bf67edd5 --- /dev/null +++ b/board/beacon/imx8mm/imx8mm_beacon.env @@ -0,0 +1,19 @@ +boot_fit=try +bootscript=echo Running bootscript from mmc ...; source +console=ttymxc1 +fdt_addr=0x45000000 +fdt_file=imx8mm-beacon-kit.dtb +finduuid=part uuid mmc ${mmcdev}:2 uuid +image=Image +initrd_addr=0x46000000 +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs} +mmcautodetect=yes +mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +mmcdev=1 +mmcpart=1 +netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; fi; +script=boot.scr diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index a5f337aa17..b2830c5223 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -36,6 +36,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_MMC2; case USB_BOOT: return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; default: return BOOT_DEVICE_NONE; } @@ -46,6 +48,11 @@ static void spl_dram_init(void) ddr_init(&dram_timing); } +void spl_board_init(void) +{ + arch_misc_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README deleted file mode 100644 index 49da03c8d8..0000000000 --- a/board/beacon/imx8mn/README +++ /dev/null @@ -1,38 +0,0 @@ -U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit - -Quick Start -=========== -- Build the ARM Trusted firmware binary -- Get ddr firmware -- Build U-Boot -- Boot - -Get and Build the ARM Trusted firmware -====================================== -Note: $(srctree) is U-Boot source directory - -$ git clone https://github.com/nxp-imx/imx-atf -$ git lf-5.10.72-2.2.0 -$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu- -$ cp build/imx8mn/release/bl31.bin $(srctree) - -Get the DDR firmware -==================== -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin -$ chmod +x firmware-imx-8.9.bin -$ ./firmware-imx-8.9 -$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree) - -Build U-Boot -============ -$ make imx8mn_beacon_defconfig -$ make CROSS_COMPILE=aarch64-linux-gnu- - -Burn U-Boot to microSD Card -=========================== -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 - -Boot -==== -Set baseboard DIP switch: -S17: 1100XXXX diff --git a/board/beacon/imx8mn/imx8mn_beacon.env b/board/beacon/imx8mn/imx8mn_beacon.env new file mode 100644 index 0000000000..ca90053d47 --- /dev/null +++ b/board/beacon/imx8mn/imx8mn_beacon.env @@ -0,0 +1,25 @@ +boot_fdt=try +bootdelay=2 +bootscript=echo Running bootscript from mmc ...; source +console=ttymxc1 +fdt_addr=0x45000000 +fdt_file=imx8mn-beacon-kit.dtb +finduuid=part uuid mmc ${mmcdev}:2 uuid +image=Image +initrd_addr=0x46000000 +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage} +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs} +mmcautodetect=yes +mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else echo wait for boot; fi; +mmcdev=1 +mmcpart=1 +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else booti; fi; +ramargs=setenv bootargs console=${console},${baudrate} root=/dev/ram rw ${optargs} +ramboot=echo Booting from RAMdisk...; run loadimage; run loadfdt; fdt addr $fdt_addr; run loadramdisk; run ramargs; booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs} +ramdisk_addr=0x46000000 +ramdiskimage=rootfs.cpio.uboot +script=boot.scr diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index bedd1e0330..26189ff66f 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -79,7 +79,7 @@ static void setup_iomux_uart(void) int board_early_init_f(void) { /* sc_ipc_t ipcHndl = 0; */ - sc_err_t scierr = 0; + int scierr; /* When start u-boot in XEN VM, directly return */ /* if (IS_ENABLED(CONFIG_XEN)) */ @@ -89,19 +89,19 @@ int board_early_init_f(void) /* Power up UART0, this is very early while power domain is not working */ scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); - if (scierr != SC_ERR_NONE) + if (scierr) return 0; /* Set UART0 clock root to 80 MHz */ sc_pm_clock_rate_t rate = 80000000; scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); - if (scierr != SC_ERR_NONE) + if (scierr) return 0; /* Enable UART0 clock root */ scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); - if (scierr != SC_ERR_NONE) + if (scierr) return 0; setup_iomux_uart(); diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index c30185e48d..2fdd95a730 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -107,6 +107,20 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[4] = BOOT_DEVICE_NONE; } +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect) +{ + const u32 boot_dev = spl_boot_device(); + int part; + + if (boot_dev == BOOT_DEVICE_MMC2) { /* eMMC */ + part = spl_mmc_emmc_boot_partition(mmc); + if (part == 1 || part == 2) /* eMMC BOOT1/BOOT2 HW partitions */ + return sect - 0x40; + } + + return sect; +} + static struct dram_timing_info *dram_timing_info[8] = { &dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */ NULL, /* 32 Gbit x16 */ diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index a0dad5f983..66d0f68cc6 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -19,7 +19,7 @@ #include <asm/arch/ddr.h> #include <asm/arch/rdc.h> #include <asm/arch/upower.h> -#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/ele_api.h> DECLARE_GLOBAL_DATA_PTR; @@ -63,9 +63,9 @@ void display_ele_fw_version(void) u32 fw_version, sha1, res; int ret; - ret = ahab_get_fw_version(&fw_version, &sha1, &res); + ret = ele_get_fw_version(&fw_version, &sha1, &res); if (ret) { - printf("ahab get firmware version failed %d, 0x%x\n", ret, res); + printf("ele get firmware version failed %d, 0x%x\n", ret, res); } else { printf("ELE firmware version %u.%u.%u-%x", (fw_version & (0x00ff0000)) >> 16, @@ -120,9 +120,19 @@ void spl_board_init(void) set_lpav_qos(); /* Enable A35 access to the CAAM */ - ret = ahab_release_caam(0x7, &res); + ret = ele_release_caam(0x7, &res); if (ret) - printf("ahab release caam failed %d, 0x%x\n", ret, res); + printf("ele release caam failed %d, 0x%x\n", ret, res); + + /* + * RNG start only available on the A1 soc revision. + * Check some JTAG register for the SoC revision. + */ + if (!is_soc_rev(CHIP_REV_1_0)) { + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + } } void board_init_f(ulong dummy) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 352ad79cb6..63883b30dd 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -20,7 +20,6 @@ #include <asm/mach-imx/mxc_i2c.h> #include <asm/arch-mx7ulp/gpio.h> #include <asm/mach-imx/syscounter.h> -#include <asm/mach-imx/s400_api.h> #include <dm/uclass.h> #include <dm/device.h> #include <dm/uclass-internal.h> diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 2777ae13bc..cff2e6a871 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -292,6 +292,7 @@ int power_init_board(void) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + unsigned char eth1addr[6]; imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); @@ -303,6 +304,11 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); + /* Get the second MAC address */ + imx_get_mac_from_fuse(1, eth1addr); + if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) + eth_env_set_enetaddr("eth1addr", eth1addr); + return 0; } diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index 6aea60ad05..241be4ee63 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -218,6 +218,11 @@ const char *eeprom_get_dtb_name(int level, char *buf, int sz) int rev_base_bom = get_bom_rev(base_info.model); snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som); + /* GW79xx baseboards have no build options */ + if (base == 79) { + base = (int)strtoul(base_info.model + 2, NULL, 10); + snprintf(buf, sz, "%s%4d-%dx", pre, base, som); + } switch (level) { case 0: /* full model (ie gw73xx-0x-a1a1) */ if (rev_base_bom) diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index 62b860610c..d19902f10e 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -16,6 +16,7 @@ extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_2gb_single_die; extern struct dram_timing_info dram_timing_2gb_dual_die; #elif CONFIG_IMX8MP +extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_4gb_dual_die; #endif diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 2e96332f8b..7bfd1b556b 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1315,6 +1315,538 @@ static struct dram_cfg_param ddr_phy_pie[] = { }; /* + * Generated code from MX8M_DDR_tool v3.30 using MX8MP Plus RPAv9 + * - 1GiB: ixm8mp-gw7020 1x Micron MT53E256M32D2DS 2-ch single-die per channel + */ +struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1203 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b0087 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x402 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0x8d }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1001 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0012 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x302 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x13 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1001 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30005 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x302 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x5 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0x599 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x3 }, + { 0x100a3, 0x2 }, + { 0x100a4, 0x5 }, + { 0x100a5, 0x4 }, + { 0x100a6, 0x7 }, + { 0x100a7, 0x6 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x3 }, + { 0x130a3, 0x4 }, + { 0x130a4, 0x5 }, + { 0x130a5, 0x2 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1gb_single_die), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1gb_single_die = { + .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), + .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_1gb_single_die), + .fsp_msg = ddr_dram_fsp_msg_1gb_single_die, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1gb_single_die), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + +/* * Generated code from MX8M_DDR_tool v3.30 using MX8M Plus RPAv7 * - 4GiB: imx8mp-gw7401 1x Micron MT53D1024M32D4DT 2-ch dual-die per channel */ diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 4eb7bdfcee..5aa209578b 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -71,6 +71,9 @@ static void spl_dram_init(int size) dram_timing = &dram_timing_2gb_dual_die; size = 2048; #elif CONFIG_IMX8MP + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; case 4096: dram_timing = &dram_timing_4gb_dual_die; break; @@ -83,9 +86,12 @@ static void spl_dram_init(int size) printf("DRAM : LPDDR4 "); if (size > 512) - printf("%d GiB\n", size / 1024); + printf("%d GiB", size / 1024); else - printf("%d MiB\n", size); + printf("%d MiB", size); + printf(" %dMT/s %dMHz\n", + dram_timing->fsp_msg[0].drate, + dram_timing->fsp_msg[0].drate / 2); ddr_init(dram_timing); } @@ -121,7 +127,8 @@ static int power_init_board(void) if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || - (!strncmp(model, "GW73", 4))) { + (!strncmp(model, "GW73", 4)) || + (!strncmp(model, "GW7905", 6))) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); @@ -132,11 +139,22 @@ static int power_init_board(void) printf("PMIC : failed probe: %d\n", ret); return ret; } - puts("PMIC : MP5416\n"); +#ifdef CONFIG_IMX8MM + puts("PMIC : MP5416 (IMX8MM)\n"); /* set VDD_ARM SW3 to 0.92V for 1.6GHz */ dm_i2c_reg_write(dev, MP5416_VSET_SW3, BIT(7) | MP5416_VSET_SW3_SVAL(920000)); +#elif CONFIG_IMX8MP + puts("PMIC : MP5416 (IMX8MP)\n"); + + /* set VDD_ARM SW3 to 0.95V for 1.6GHz */ + dm_i2c_reg_write(dev, MP5416_VSET_SW3, + BIT(7) | MP5416_VSET_SW3_SVAL(950000)); + /* set VDD_SOC SW1 to 0.95V for 1.6GHz */ + dm_i2c_reg_write(dev, MP5416_VSET_SW1, + BIT(7) | MP5416_VSET_SW1_SVAL(950000)); +#endif } else if (!strncmp(model, "GW74", 4)) { @@ -327,6 +345,21 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) } } +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) +{ + if (!IS_SD(mmc)) { + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: + case 2: + if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) + raw_sect -= 32 * 2; + break; + } + } + + return raw_sect; +} + const char *spl_board_loader_name(u32 boot_device) { switch (boot_device) { @@ -340,3 +373,8 @@ const char *spl_board_loader_name(u32 boot_device) return NULL; } } + +void spl_board_init(void) +{ + arch_misc_init(); +} diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index ca62f0be6d..a39ae58c8a 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -6,9 +6,12 @@ #include <fdt_support.h> #include <init.h> #include <led.h> +#include <mmc.h> #include <miiphy.h> +#include <mmc.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> #include "eeprom.h" @@ -17,7 +20,7 @@ int board_phys_sdram_size(phys_size_t *size) if (!size) return -EINVAL; - *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + *size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE); return 0; } @@ -93,10 +96,12 @@ int board_init(void) int board_late_init(void) { const char *str; + struct mmc *mmc = NULL; char env[32]; int ret, i; u8 enetaddr[6]; char fdt[64]; + int bootdev; /* Set board serial/model */ if (!env_get("serial#")) @@ -131,6 +136,74 @@ int board_late_init(void) i++; } while (!ret); + /* + * set bootdev/bootblk/bootpart (used in firmware_update script) + * dynamically depending on boot device and SoC + */ + bootdev = -1; + switch (get_boot_device()) { + case SD1_BOOT: + case MMC1_BOOT: /* SDHC1 */ + bootdev = 0; + break; + case SD2_BOOT: + case MMC2_BOOT: /* SDHC2 */ + bootdev = 1; + break; + case SD3_BOOT: + case MMC3_BOOT: /* SDHC3 */ + bootdev = 2; + break; + default: + bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */ + break; + } + if (bootdev != -1) + mmc = find_mmc_device(bootdev); + if (mmc) { + int bootblk; + + if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) + bootblk = 32 * SZ_1K / 512; + else + bootblk = 33 * SZ_1K / 512; + mmc_init(mmc); + if (!IS_SD(mmc)) { + int bootpart; + + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: /* boot0 */ + bootpart = 1; + break; + case 2: /* boot1 */ + bootpart = 2; + break; + case 7: /* user */ + default: + bootpart = 0; + break; + } + /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */ + if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) && + (bootpart == 1 || bootpart == 2)) + bootblk = 0; + env_set_hex("bootpart", bootpart); + env_set_hex("bootblk", bootblk); + } else { /* SD */ + env_set("bootpart", ""); + env_set_hex("bootblk", bootblk); + } + env_set_hex("dev", bootdev); + } + + /* override soc=imx8m to provide a more specific soc name */ + if (IS_ENABLED(CONFIG_IMX8MN)) + env_set("soc", "imx8mn"); + else if (IS_ENABLED(CONFIG_IMX8MP)) + env_set("soc", "imx8mp"); + else if (IS_ENABLED(CONFIG_IMX8MM)) + env_set("soc", "imx8mm"); + return 0; } @@ -139,6 +212,20 @@ int board_mmc_get_env_dev(int devno) return devno; } +uint mmc_get_env_part(struct mmc *mmc) +{ + if (!IS_SD(mmc)) { + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: + return 1; + case 2: + return 2; + } + } + + return 0; +} + int ft_board_setup(void *fdt, struct bd_info *bd) { const char *base_model = eeprom_get_baseboard_model(); diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env index f81804ca12..a0d6c43325 100644 --- a/board/gateworks/venice/venice.env +++ b/board/gateworks/venice/venice.env @@ -8,11 +8,11 @@ bootm_size=0x10000000 dev=2 preboot=gsc wd-disable console=ttymxc1,115200 -update_firmware=tftpboot $loadaddr $image && +update_firmware=tftpboot $loadaddr $dir/venice-$soc-flash.bin && setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 && - mmc dev $dev && - mmc write $loadaddr $splblk $blkcnt + mmc dev $dev $bootpart && + mmc write $loadaddr $bootblk $blkcnt loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1; then echo loaded $fdt_file1; elif $fsload $fdt_addr_r $dir/$fdt_file2; @@ -31,4 +31,3 @@ update_rootfs=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize 100000 1000000 update_all=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize -erase_env=mmc dev $dev; mmc erase 0x7f08 0x40 diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index ddb509eb66..8dcc2ea54f 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -37,7 +37,7 @@ struct efi_capsule_update_info update_info = { int board_phys_sdram_size(phys_size_t *size) { - u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR); + u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR); if (ddr_size == 4) { *size = 0x100000000; diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 3a919d0a9c..b49373442a 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -106,7 +106,7 @@ static void spl_dram_init(void) } gd->ram_size = size; - writel(size, M4_BOOTROM_BASE_ADDR); + writel(size, MCU_BOOTROM_BASE_ADDR); } int do_board_detect(void) diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 38e841c5f6..e4d2eb65cc 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -62,6 +62,7 @@ static void init_clocks(void) void board_init_f(ulong arg) { init_clocks(); + spl_early_init(); preloader_console_init(); } @@ -203,5 +204,22 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif - +/* + * NOTE: + * + * IMX28 clock "stub" DM driver! + * + * Only used for SPL stage, which is NOT using DM; serial and + * eMMC configuration. + */ +static const struct udevice_id imx28_clk_ids[] = { + { .compatible = "fsl,imx28-clkctrl", }, + { } +}; + +U_BOOT_DRIVER(fsl_imx28_clkctrl) = { + .name = "fsl_imx28_clkctrl", + .id = UCLASS_CLK, + .of_match = imx28_clk_ids, +}; #endif /* CONFIG_SPL_BUILD */ diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c b/board/phytec/phycore_imx8mm/lpddr4_timing.c index 811ac26415..f5a2f3268b 100644 --- a/board/phytec/phycore_imx8mm/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Copyright 2019 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH * * Generated code from MX8M_DDR_tool */ @@ -13,22 +14,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400304, 0x1}, {0x3d400030, 0x1}, {0x3d400000, 0xa1080020}, - {0x3d400020, 0x223}, + {0x3d400020, 0x222}, {0x3d400024, 0x3a980}, - {0x3d400064, 0x5b00d2}, + {0x3d400064, 0x2d00d2}, {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, {0x3d4000e0, 0x310000}, {0x3d4000e8, 0x66004d}, {0x3d4000ec, 0x16004d}, - {0x3d400100, 0x191e1920}, + {0x3d400100, 0x191e0c20}, {0x3d400104, 0x60630}, {0x3d40010c, 0xb0b000}, {0x3d400110, 0xe04080e}, {0x3d400114, 0x2040c0c}, {0x3d400118, 0x1010007}, - {0x3d40011c, 0x401}, + {0x3d40011c, 0x402}, {0x3d400130, 0x20600}, {0x3d400134, 0xc100002}, {0x3d400138, 0xd8}, @@ -45,7 +46,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d4001b0, 0x11}, {0x3d4001c0, 0x1}, {0x3d4001c4, 0x1}, - {0x3d4000f4, 0xc99}, + {0x3d4000f4, 0x699}, {0x3d400108, 0x70e1617}, {0x3d400200, 0x1f}, {0x3d40020c, 0x0}, @@ -53,6 +54,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400204, 0x80808}, {0x3d400214, 0x7070707}, {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, {0x3d400250, 0x29001701}, {0x3d400254, 0x2c}, {0x3d40025c, 0x4000030}, @@ -64,22 +66,22 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400498, 0x620096}, {0x3d40049c, 0x1100e07}, {0x3d4004a0, 0xc8012c}, - {0x3d402020, 0x21}, + {0x3d402020, 0x20}, {0x3d402024, 0x7d00}, {0x3d402050, 0x20d040}, - {0x3d402064, 0xc001c}, + {0x3d402064, 0x6001c}, {0x3d4020dc, 0x840000}, {0x3d4020e0, 0x310000}, {0x3d4020e8, 0x66004d}, {0x3d4020ec, 0x16004d}, - {0x3d402100, 0xa040305}, + {0x3d402100, 0xa040105}, {0x3d402104, 0x30407}, {0x3d402108, 0x203060b}, {0x3d40210c, 0x505000}, {0x3d402110, 0x2040202}, {0x3d402114, 0x2030202}, {0x3d402118, 0x1010004}, - {0x3d40211c, 0x301}, + {0x3d40211c, 0x302}, {0x3d402130, 0x20300}, {0x3d402134, 0xa100002}, {0x3d402138, 0x1d}, @@ -88,8 +90,8 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d402190, 0x3818200}, {0x3d402194, 0x80303}, {0x3d4021b4, 0x100}, - {0x3d4020f4, 0xc99}, - {0x3d403020, 0x21}, + {0x3d4020f4, 0x599}, + {0x3d403020, 0x20}, {0x3d403024, 0x1f40}, {0x3d403050, 0x20d040}, {0x3d403064, 0x30007}, @@ -104,7 +106,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403110, 0x2040202}, {0x3d403114, 0x2030202}, {0x3d403118, 0x1010004}, - {0x3d40311c, 0x301}, + {0x3d40311c, 0x302}, {0x3d403130, 0x20300}, {0x3d403134, 0xa100002}, {0x3d403138, 0x8}, @@ -113,7 +115,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403190, 0x3818200}, {0x3d403194, 0x80303}, {0x3d4031b4, 0x100}, - {0x3d4030f4, 0xc99}, + {0x3d4030f4, 0x599}, {0x3d400028, 0x0}, }; @@ -201,8 +203,8 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x220024, 0x1ab}, {0x2003a, 0x0}, {0x20056, 0x3}, - {0x120056, 0xa}, - {0x220056, 0xa}, + {0x120056, 0x3}, + {0x220056, 0x3}, {0x1004d, 0xe00}, {0x1014d, 0xe00}, {0x1104d, 0xe00}, @@ -323,727 +325,726 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { /* ddr phy trained csr */ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, + {0x200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x200cb, 0x0}, + {0x10043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x10143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x11043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x11143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x12043, 0x0}, + {0x112043, 0x0}, + {0x212043, 0x0}, + {0x12143, 0x0}, + {0x112143, 0x0}, + {0x212143, 0x0}, + {0x13043, 0x0}, + {0x113043, 0x0}, + {0x213043, 0x0}, + {0x13143, 0x0}, + {0x113143, 0x0}, + {0x213143, 0x0}, + {0x80, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x1080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x2080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x3080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x4080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x5080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x6080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x7080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x8080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x9080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x10080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x10180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x11080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x11180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x12080, 0x0}, + {0x112080, 0x0}, + {0x212080, 0x0}, + {0x12180, 0x0}, + {0x112180, 0x0}, + {0x212180, 0x0}, + {0x13080, 0x0}, + {0x113080, 0x0}, + {0x213080, 0x0}, + {0x13180, 0x0}, + {0x113180, 0x0}, + {0x213180, 0x0}, + {0x10081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x10181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x11081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x11181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x12081, 0x0}, + {0x112081, 0x0}, + {0x212081, 0x0}, + {0x12181, 0x0}, + {0x112181, 0x0}, + {0x212181, 0x0}, + {0x13081, 0x0}, + {0x113081, 0x0}, + {0x213081, 0x0}, + {0x13181, 0x0}, + {0x113181, 0x0}, + {0x213181, 0x0}, + {0x100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x120d0, 0x0}, + {0x1120d0, 0x0}, + {0x2120d0, 0x0}, + {0x121d0, 0x0}, + {0x1121d0, 0x0}, + {0x2121d0, 0x0}, + {0x130d0, 0x0}, + {0x1130d0, 0x0}, + {0x2130d0, 0x0}, + {0x131d0, 0x0}, + {0x1131d0, 0x0}, + {0x2131d0, 0x0}, + {0x100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x120d1, 0x0}, + {0x1120d1, 0x0}, + {0x2120d1, 0x0}, + {0x121d1, 0x0}, + {0x1121d1, 0x0}, + {0x2121d1, 0x0}, + {0x130d1, 0x0}, + {0x1130d1, 0x0}, + {0x2130d1, 0x0}, + {0x131d1, 0x0}, + {0x1131d1, 0x0}, + {0x2131d1, 0x0}, + {0x10068, 0x0}, + {0x10168, 0x0}, + {0x10268, 0x0}, + {0x10368, 0x0}, + {0x10468, 0x0}, + {0x10568, 0x0}, + {0x10668, 0x0}, + {0x10768, 0x0}, + {0x10868, 0x0}, + {0x11068, 0x0}, + {0x11168, 0x0}, + {0x11268, 0x0}, + {0x11368, 0x0}, + {0x11468, 0x0}, + {0x11568, 0x0}, + {0x11668, 0x0}, + {0x11768, 0x0}, + {0x11868, 0x0}, + {0x12068, 0x0}, + {0x12168, 0x0}, + {0x12268, 0x0}, + {0x12368, 0x0}, + {0x12468, 0x0}, + {0x12568, 0x0}, + {0x12668, 0x0}, + {0x12768, 0x0}, + {0x12868, 0x0}, + {0x13068, 0x0}, + {0x13168, 0x0}, + {0x13268, 0x0}, + {0x13368, 0x0}, + {0x13468, 0x0}, + {0x13568, 0x0}, + {0x13668, 0x0}, + {0x13768, 0x0}, + {0x13868, 0x0}, + {0x10069, 0x0}, + {0x10169, 0x0}, + {0x10269, 0x0}, + {0x10369, 0x0}, + {0x10469, 0x0}, + {0x10569, 0x0}, + {0x10669, 0x0}, + {0x10769, 0x0}, + {0x10869, 0x0}, + {0x11069, 0x0}, + {0x11169, 0x0}, + {0x11269, 0x0}, + {0x11369, 0x0}, + {0x11469, 0x0}, + {0x11569, 0x0}, + {0x11669, 0x0}, + {0x11769, 0x0}, + {0x11869, 0x0}, + {0x12069, 0x0}, + {0x12169, 0x0}, + {0x12269, 0x0}, + {0x12369, 0x0}, + {0x12469, 0x0}, + {0x12569, 0x0}, + {0x12669, 0x0}, + {0x12769, 0x0}, + {0x12869, 0x0}, + {0x13069, 0x0}, + {0x13169, 0x0}, + {0x13269, 0x0}, + {0x13369, 0x0}, + {0x13469, 0x0}, + {0x13569, 0x0}, + {0x13669, 0x0}, + {0x13769, 0x0}, + {0x13869, 0x0}, + {0x1008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x1018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x1108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x1118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x1208c, 0x0}, + {0x11208c, 0x0}, + {0x21208c, 0x0}, + {0x1218c, 0x0}, + {0x11218c, 0x0}, + {0x21218c, 0x0}, + {0x1308c, 0x0}, + {0x11308c, 0x0}, + {0x21308c, 0x0}, + {0x1318c, 0x0}, + {0x11318c, 0x0}, + {0x21318c, 0x0}, + {0x1008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x1018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x1108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x1118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x1208d, 0x0}, + {0x11208d, 0x0}, + {0x21208d, 0x0}, + {0x1218d, 0x0}, + {0x11218d, 0x0}, + {0x21218d, 0x0}, + {0x1308d, 0x0}, + {0x11308d, 0x0}, + {0x21308d, 0x0}, + {0x1318d, 0x0}, + {0x11318d, 0x0}, + {0x21318d, 0x0}, + {0x100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x120c0, 0x0}, + {0x1120c0, 0x0}, + {0x2120c0, 0x0}, + {0x121c0, 0x0}, + {0x1121c0, 0x0}, + {0x2121c0, 0x0}, + {0x122c0, 0x0}, + {0x1122c0, 0x0}, + {0x2122c0, 0x0}, + {0x123c0, 0x0}, + {0x1123c0, 0x0}, + {0x2123c0, 0x0}, + {0x124c0, 0x0}, + {0x1124c0, 0x0}, + {0x2124c0, 0x0}, + {0x125c0, 0x0}, + {0x1125c0, 0x0}, + {0x2125c0, 0x0}, + {0x126c0, 0x0}, + {0x1126c0, 0x0}, + {0x2126c0, 0x0}, + {0x127c0, 0x0}, + {0x1127c0, 0x0}, + {0x2127c0, 0x0}, + {0x128c0, 0x0}, + {0x1128c0, 0x0}, + {0x2128c0, 0x0}, + {0x130c0, 0x0}, + {0x1130c0, 0x0}, + {0x2130c0, 0x0}, + {0x131c0, 0x0}, + {0x1131c0, 0x0}, + {0x2131c0, 0x0}, + {0x132c0, 0x0}, + {0x1132c0, 0x0}, + {0x2132c0, 0x0}, + {0x133c0, 0x0}, + {0x1133c0, 0x0}, + {0x2133c0, 0x0}, + {0x134c0, 0x0}, + {0x1134c0, 0x0}, + {0x2134c0, 0x0}, + {0x135c0, 0x0}, + {0x1135c0, 0x0}, + {0x2135c0, 0x0}, + {0x136c0, 0x0}, + {0x1136c0, 0x0}, + {0x2136c0, 0x0}, + {0x137c0, 0x0}, + {0x1137c0, 0x0}, + {0x2137c0, 0x0}, + {0x138c0, 0x0}, + {0x1138c0, 0x0}, + {0x2138c0, 0x0}, + {0x100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x120c1, 0x0}, + {0x1120c1, 0x0}, + {0x2120c1, 0x0}, + {0x121c1, 0x0}, + {0x1121c1, 0x0}, + {0x2121c1, 0x0}, + {0x122c1, 0x0}, + {0x1122c1, 0x0}, + {0x2122c1, 0x0}, + {0x123c1, 0x0}, + {0x1123c1, 0x0}, + {0x2123c1, 0x0}, + {0x124c1, 0x0}, + {0x1124c1, 0x0}, + {0x2124c1, 0x0}, + {0x125c1, 0x0}, + {0x1125c1, 0x0}, + {0x2125c1, 0x0}, + {0x126c1, 0x0}, + {0x1126c1, 0x0}, + {0x2126c1, 0x0}, + {0x127c1, 0x0}, + {0x1127c1, 0x0}, + {0x2127c1, 0x0}, + {0x128c1, 0x0}, + {0x1128c1, 0x0}, + {0x2128c1, 0x0}, + {0x130c1, 0x0}, + {0x1130c1, 0x0}, + {0x2130c1, 0x0}, + {0x131c1, 0x0}, + {0x1131c1, 0x0}, + {0x2131c1, 0x0}, + {0x132c1, 0x0}, + {0x1132c1, 0x0}, + {0x2132c1, 0x0}, + {0x133c1, 0x0}, + {0x1133c1, 0x0}, + {0x2133c1, 0x0}, + {0x134c1, 0x0}, + {0x1134c1, 0x0}, + {0x2134c1, 0x0}, + {0x135c1, 0x0}, + {0x1135c1, 0x0}, + {0x2135c1, 0x0}, + {0x136c1, 0x0}, + {0x1136c1, 0x0}, + {0x2136c1, 0x0}, + {0x137c1, 0x0}, + {0x1137c1, 0x0}, + {0x2137c1, 0x0}, + {0x138c1, 0x0}, + {0x1138c1, 0x0}, + {0x2138c1, 0x0}, + {0x10020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x11020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x12020, 0x0}, + {0x112020, 0x0}, + {0x212020, 0x0}, + {0x13020, 0x0}, + {0x113020, 0x0}, + {0x213020, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x20074, 0x0}, + {0x100aa, 0x0}, + {0x110aa, 0x0}, + {0x120aa, 0x0}, + {0x130aa, 0x0}, + {0x20010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x20011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x120ae, 0x0}, + {0x1120ae, 0x0}, + {0x2120ae, 0x0}, + {0x120af, 0x0}, + {0x1120af, 0x0}, + {0x2120af, 0x0}, + {0x130ae, 0x0}, + {0x1130ae, 0x0}, + {0x2130ae, 0x0}, + {0x130af, 0x0}, + {0x1130af, 0x0}, + {0x2130af, 0x0}, + {0x20020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x130a0, 0x0}, + {0x130a1, 0x0}, + {0x130a2, 0x0}, + {0x130a3, 0x0}, + {0x130a4, 0x0}, + {0x130a5, 0x0}, + {0x130a6, 0x0}, + {0x130a7, 0x0}, + {0x2007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x2007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x400fd, 0x0}, + {0x400c0, 0x0}, + {0x90201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x90202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x90203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x90205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x90206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x90207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x90208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x10062, 0x0}, + {0x10162, 0x0}, + {0x10262, 0x0}, + {0x10362, 0x0}, + {0x10462, 0x0}, + {0x10562, 0x0}, + {0x10662, 0x0}, + {0x10762, 0x0}, + {0x10862, 0x0}, + {0x11062, 0x0}, + {0x11162, 0x0}, + {0x11262, 0x0}, + {0x11362, 0x0}, + {0x11462, 0x0}, + {0x11562, 0x0}, + {0x11662, 0x0}, + {0x11762, 0x0}, + {0x11862, 0x0}, + {0x12062, 0x0}, + {0x12162, 0x0}, + {0x12262, 0x0}, + {0x12362, 0x0}, + {0x12462, 0x0}, + {0x12562, 0x0}, + {0x12662, 0x0}, + {0x12762, 0x0}, + {0x12862, 0x0}, + {0x13062, 0x0}, + {0x13162, 0x0}, + {0x13262, 0x0}, + {0x13362, 0x0}, + {0x13462, 0x0}, + {0x13562, 0x0}, + {0x13662, 0x0}, + {0x13762, 0x0}, + {0x13862, 0x0}, + {0x20077, 0x0}, + {0x10001, 0x0}, + {0x11001, 0x0}, + {0x12001, 0x0}, + {0x13001, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x10030, 0x0}, + {0x10130, 0x0}, + {0x10230, 0x0}, + {0x10330, 0x0}, + {0x10430, 0x0}, + {0x10530, 0x0}, + {0x10630, 0x0}, + {0x10730, 0x0}, + {0x10830, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, + {0x11030, 0x0}, + {0x11130, 0x0}, + {0x11230, 0x0}, + {0x11330, 0x0}, + {0x11430, 0x0}, + {0x11530, 0x0}, + {0x11630, 0x0}, + {0x11730, 0x0}, + {0x11830, 0x0}, + {0x12040, 0x0}, + {0x12140, 0x0}, + {0x12240, 0x0}, + {0x12340, 0x0}, + {0x12440, 0x0}, + {0x12540, 0x0}, + {0x12640, 0x0}, + {0x12740, 0x0}, + {0x12840, 0x0}, + {0x12030, 0x0}, + {0x12130, 0x0}, + {0x12230, 0x0}, + {0x12330, 0x0}, + {0x12430, 0x0}, + {0x12530, 0x0}, + {0x12630, 0x0}, + {0x12730, 0x0}, + {0x12830, 0x0}, + {0x13040, 0x0}, + {0x13140, 0x0}, + {0x13240, 0x0}, + {0x13340, 0x0}, + {0x13440, 0x0}, + {0x13540, 0x0}, + {0x13640, 0x0}, + {0x13740, 0x0}, + {0x13840, 0x0}, + {0x13030, 0x0}, + {0x13130, 0x0}, + {0x13230, 0x0}, + {0x13330, 0x0}, + {0x13430, 0x0}, + {0x13530, 0x0}, + {0x13630, 0x0}, + {0x13730, 0x0}, + {0x13830, 0x0}, }; - /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { {0xd0000, 0x0}, @@ -1054,7 +1055,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { {0x54008, 0x131f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x2dd4}, {0x5401a, 0x31}, @@ -1094,7 +1094,6 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1134,7 +1133,6 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1200,7 +1198,7 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0x5403b, 0x4d}, {0x5403c, 0x4d}, {0x5403d, 0x1600}, - { 0xd0000, 0x1 }, + {0xd0000, 0x1}, }; /* DRAM PHY init engine image */ @@ -1693,15 +1691,15 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x400d6, 0x20a}, {0x400d7, 0x20b}, {0x2003a, 0x2}, - {0x2000b, 0x5d}, + {0x2000b, 0x34b}, {0x2000c, 0xbb}, {0x2000d, 0x753}, {0x2000e, 0x2c}, - {0x12000b, 0xc}, + {0x12000b, 0x70}, {0x12000c, 0x19}, {0x12000d, 0xfa}, {0x12000e, 0x10}, - {0x22000b, 0x3}, + {0x22000b, 0x1c}, {0x22000c, 0x6}, {0x22000d, 0x3e}, {0x22000e, 0x10}, @@ -1842,5 +1840,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 3000, 400, 100,}, }; diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index a0c62e0fc4..924c88e8fa 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -147,7 +147,7 @@ static void enet_device_phy_reset(void) int setup_gpr_fec(void) { sc_ipc_t ipc_handle = -1; - sc_err_t err = 0; + int err = 0; unsigned int test; /* @@ -175,35 +175,35 @@ int setup_gpr_fec(void) */ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test); err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1); - if (err != SC_ERR_NONE) + if (err) printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125); sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test); diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 951e3e1985..2be3206f78 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -54,7 +54,7 @@ int board_early_init_f(void) int board_phys_sdram_size(phys_size_t *size) { - int ddr_size = readl(M4_BOOTROM_BASE_ADDR); + int ddr_size = readl(MCU_BOOTROM_BASE_ADDR); if (ddr_size == 0x4) { *size = 0x100000000; diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index 8b853a914e..2afb4d3760 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -89,7 +89,7 @@ static void spl_dram_init(void) printf("%s: LPDDR4 %d GiB\n", __func__, size); ddr_init(dram_timing); - writel(size, M4_BOOTROM_BASE_ADDR); + writel(size, MCU_BOOTROM_BASE_ADDR); } #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index aa76c486ee..e2bbaba8b8 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -85,18 +85,18 @@ static void setup_iomux_uart(void) static uint32_t do_get_tdx_user_fuse(int a, int b) { - sc_err_t sciErr; + int sciErr; u32 val_a = 0; u32 val_b = 0; sciErr = sc_misc_otp_fuse_read(-1, a, &val_a); - if (sciErr != SC_ERR_NONE) { + if (sciErr) { printf("Error reading out user fuse %d\n", a); return 0; } sciErr = sc_misc_otp_fuse_read(-1, b, &val_b); - if (sciErr != SC_ERR_NONE) { + if (sciErr) { printf("Error reading out user fuse %d\n", b); return 0; } @@ -131,9 +131,9 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, { u32 is_quadplus = 0, val = 0; struct tdx_user_fuses tdxramfuses; - sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); + int scierr = sc_misc_otp_fuse_read(-1, 6, &val); - if (scierr == SC_ERR_NONE) { + if (scierr) { /* QP has one A72 core disabled */ is_quadplus = ((val >> 4) & 0x3) != 0x0; } diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 52fc7a391b..6c0b09787c 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -12,6 +12,7 @@ #include <asm/arch/imx8-pins.h> #include <asm/arch/iomux.h> #include <firmware/imx/sci/sci.h> +#include <asm/arch/snvs_security_sc.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/io.h> @@ -43,9 +44,9 @@ static void setup_iomux_uart(void) static int is_imx8dx(void) { u32 val = 0; - sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val); + int sc_err = sc_misc_otp_fuse_read(-1, 6, &val); - if (sc_err == SC_ERR_NONE) { + if (sc_err) { /* DX has two A35 cores disabled */ return (val & 0xf) != 0x0; } @@ -70,7 +71,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, int board_early_init_f(void) { sc_pm_clock_rate_t rate; - sc_err_t err = 0; + int err; /* * This works around that having only UART3 up the baudrate is 1.2M @@ -78,13 +79,13 @@ int board_early_init_f(void) */ rate = 80000000; err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); - if (err != SC_ERR_NONE) + if (err) return 0; /* Set UART3 clock root to 80 MHz and enable it */ rate = SC_80MHZ; err = sc_pm_setup_uart(SC_R_UART_3, rate); - if (err != SC_ERR_NONE) + if (err) return 0; setup_iomux_uart(); @@ -139,6 +140,13 @@ int board_init(void) { board_gpio_init(); + if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } + return 0; } @@ -170,6 +178,8 @@ int board_late_init(void) env_set("board_rev", "v1.0"); #endif + build_info(); + select_dt_from_module_version(); return 0; diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 65e0e9a156..677caa4a4e 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -767,8 +767,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, /* * MDMISC mirroring interleaved (row/bank/col) */ -/* TODO: check what the RALAT field does */ -MX6_MMDC_P0_MDMISC, 0x00081740, +MX6_MMDC_P0_MDMISC, 0x000b17c0, /* * MDSCR con_req @@ -900,8 +899,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, /* * MDMISC mirroring interleaved (row/bank/col) */ -/* TODO: check what the RALAT field does */ -MX6_MMDC_P0_MDMISC, 0x00081740, +MX6_MMDC_P0_MDMISC, 0x000b17c0, /* * MDSCR con_req diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 11f4d5e14a..e513f4a291 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -139,6 +139,7 @@ const struct toradex_som toradex_modules[] = { [66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, [67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, [68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, }; const char * const toradex_carrier_boards[] = { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 32e4c6f687..45fa04ca38 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -94,6 +94,8 @@ enum { VERDIN_IMX8MPQ_8GB_WIFI_BT, APALIS_IMX8QM_8GB_WIFI_BT_IT, VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN, + /* 69 */ + VERDIN_IMX8MPQ_8GB_WIFI_BT_IT = 70, /* 70 */ }; enum { diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index 974b3a1032..b0f4329253 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -3,7 +3,6 @@ M: Marcel Ziswiler <marcel.ziswiler@toradex.com> W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained F: arch/arm/dts/imx8mm-verdin.dtsi -F: arch/arm/dts/imx8mm-verdin-dahlia.dtsi F: arch/arm/dts/imx8mm-verdin-dev.dtsi F: arch/arm/dts/imx8mm-verdin-wifi.dtsi F: arch/arm/dts/imx8mm-verdin-wifi-dev.dts diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS index cff3c50383..ea04a83926 100644 --- a/board/toradex/verdin-imx8mp/MAINTAINERS +++ b/board/toradex/verdin-imx8mp/MAINTAINERS @@ -1,6 +1,5 @@ Verdin iMX8M Plus F: arch/arm/dts/imx8mp-verdin.dtsi -F: arch/arm/dts/imx8mp-verdin-dahlia.dtsi F: arch/arm/dts/imx8mp-verdin-dev.dtsi F: arch/arm/dts/imx8mp-verdin-wifi.dtsi F: arch/arm/dts/imx8mp-verdin-wifi-dev.dts diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 5490d3ed44..e16a771e3e 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -81,7 +81,8 @@ static void select_dt_from_module_version(void) */ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT); + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT); } if (is_wifi) diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index d40f4d0176..61b9455a8f 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -1,11 +1,50 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2021 Collabora Ltd. + * Copyright 2018-2020 Variscite Ltd. + * Copyright 2023 DimOnOff Inc. */ #include <common.h> +#include <dm.h> #include <env.h> +#include <fdtdec.h> +#include <fdt_support.h> +#include <i2c_eeprom.h> +#include <malloc.h> #include <asm/io.h> +#include <asm/global_data.h> +#include <dt-bindings/gpio/gpio.h> +#include <linux/libfdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Optional SOM features flags. */ +#define VAR_EEPROM_F_WIFI BIT(0) +#define VAR_EEPROM_F_ETH BIT(1) /* Ethernet PHY on SOM. */ +#define VAR_EEPROM_F_AUDIO BIT(2) +#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ only */ +#define VAR_EEPROM_F_MX8Q_SOC_ID BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */ +#define VAR_EEPROM_F_NAND BIT(4) + +#define VAR_IMX8_EEPROM_MAGIC 0x384D /* "8M" */ + +/* Number of DRAM adjustment tables. */ +#define DRAM_TABLES_NUM 7 + +struct var_imx8_eeprom_info { + u16 magic; + u8 partnumber[3]; /* Part number */ + u8 assembly[10]; /* Assembly number */ + u8 date[9]; /* Build date */ + u8 mac[6]; /* MAC address */ + u8 somrev; + u8 eeprom_version; + u8 features; /* SOM features */ + u8 dramsize; /* DRAM size */ + u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */ + u8 partnumber2[5]; /* Part number 2 */ +} __packed; static void setup_fec(void) { @@ -28,3 +67,178 @@ int board_mmc_get_env_dev(int devno) { return devno; } + +#if !defined(CONFIG_SPL_BUILD) + +#if defined(CONFIG_DISPLAY_BOARDINFO) + +static void display_som_infos(struct var_imx8_eeprom_info *info) +{ + char partnumber[sizeof(info->partnumber) + + sizeof(info->partnumber2) + 1]; + char assembly[sizeof(info->assembly) + 1]; + char date[sizeof(info->date) + 1]; + + /* Read first part of P/N. */ + memcpy(partnumber, info->partnumber, sizeof(info->partnumber)); + + /* Read second part of P/N. */ + if (info->eeprom_version >= 3) + memcpy(partnumber + sizeof(info->partnumber), info->partnumber2, + sizeof(info->partnumber2)); + + memcpy(assembly, info->assembly, sizeof(info->assembly)); + memcpy(date, info->date, sizeof(info->date)); + + /* Make sure strings are null terminated. */ + partnumber[sizeof(partnumber) - 1] = '\0'; + assembly[sizeof(assembly) - 1] = '\0'; + date[sizeof(date) - 1] = '\0'; + + printf("SOM board: P/N: %s, Assy: %s, Date: %s\n" + " Wifi: %s, EthPhy: %s, Rev: %d\n", + partnumber, assembly, date, + info->features & VAR_EEPROM_F_WIFI ? "yes" : "no", + info->features & VAR_EEPROM_F_ETH ? "yes" : "no", + info->somrev); +} + +static int var_read_som_eeprom(struct var_imx8_eeprom_info *info) +{ + const char *path = "eeprom-som"; + struct udevice *dev; + int ret, off; + + off = fdt_path_offset(gd->fdt_blob, path); + if (off < 0) { + pr_err("%s: fdt_path_offset() failed: %d\n", __func__, off); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + pr_err("%s: uclass_get_device_by_of_offset() failed: %d\n", + __func__, ret); + return ret; + } + + ret = i2c_eeprom_read(dev, 0, (uint8_t *)info, + sizeof(struct var_imx8_eeprom_info)); + if (ret) { + pr_err("%s: i2c_eeprom_read() failed: %d\n", __func__, ret); + return ret; + } + + if (htons(info->magic) != VAR_IMX8_EEPROM_MAGIC) { + /* Do not fail if the content is invalid */ + pr_err("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n", + htons(info->magic), VAR_IMX8_EEPROM_MAGIC); + } + + return 0; +} + +int checkboard(void) +{ + int rc; + struct var_imx8_eeprom_info *info; + + info = malloc(sizeof(struct var_imx8_eeprom_info)); + if (!info) + return -ENOMEM; + + rc = var_read_som_eeprom(info); + if (rc) + return rc; + + display_som_infos(info); + +#if defined(CONFIG_BOARD_TYPES) + gd->board_type = info->features; +#endif /* CONFIG_BOARD_TYPES */ + + return 0; +} + +#endif /* CONFIG_DISPLAY_BOARDINFO */ + +static int insert_gpios_prop(void *blob, int node, const char *prop, + unsigned int phandle, u32 gpio, u32 flags) +{ + fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio), + cpu_to_fdt32(flags) }; + return fdt_setprop(blob, node, prop, &val, sizeof(val)); +} + +static int configure_phy_reset_gpios(void *blob) +{ + int node; + int phynode; + int ret; + u32 handle; + u32 gpio; + u32 flags; + char path[1024]; + const char *eth_alias = "ethernet0"; + + snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4", + fdt_get_alias(blob, eth_alias)); + + phynode = fdt_path_offset(blob, path); + if (phynode < 0) { + pr_err("%s(): unable to locate PHY node: %s\n", __func__, path); + return 0; + } + + if (gd_board_type() & VAR_EEPROM_F_ETH) { + snprintf(path, sizeof(path), "%s", + fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */ + gpio = 9; + flags = GPIO_ACTIVE_LOW; + } else { + snprintf(path, sizeof(path), "%s/gpio@20", + fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */ + gpio = 5; + flags = GPIO_ACTIVE_HIGH; + } + + node = fdt_path_offset(blob, path); + if (node < 0) { + pr_err("%s(): unable to locate GPIO node: %s\n", __func__, + path); + return 0; + } + + handle = fdt_get_phandle(blob, node); + if (handle < 0) { + pr_err("%s(): unable to locate GPIO controller handle: %s\n", + __func__, path); + } + + ret = insert_gpios_prop(blob, phynode, "reset-gpios", + handle, gpio, flags); + if (ret < 0) { + pr_err("%s(): failed to set reset-gpios property\n", __func__); + return ret; + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *blob) +{ + /* Fix U-Boot device tree: */ + return configure_phy_reset_gpios(blob); +} +#endif /* CONFIG_OF_BOARD_FIXUP */ + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Fix kernel device tree: */ + return configure_phy_reset_gpios(blob); +} +#endif /* CONFIG_OF_BOARD_SETUP */ + +#endif /* CONFIG_SPL_BUILD */ |