diff options
| author | Tom Rini <trini@konsulko.com> | 2020-07-08 05:58:18 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-08 05:58:18 +0300 |
| commit | 0b59138690a93f3d880be3d5aa675f7219376e58 (patch) | |
| tree | b139bf8d951a50c2196f3f36dc2f5ab2f3bb1cc7 /board | |
| parent | 1e88e78177da80fa8e9fa9fc7613657478d61d1e (diff) | |
| parent | 9b9f10e3ccded02443162980d34be517886b0645 (diff) | |
| download | u-boot-0b59138690a93f3d880be3d5aa675f7219376e58.tar.xz | |
Merge branch '2020-07-07-misc-new-features'
- Improve s700 SoC support
- Fix building with clang on ARM.
- Juno platform updates
- fs/dm cmd improvements
- Other assorted improvements / fixes
Diffstat (limited to 'board')
| -rw-r--r-- | board/armltd/vexpress64/pcie.c | 14 | ||||
| -rw-r--r-- | board/armltd/vexpress64/vexpress64.c | 2 |
2 files changed, 11 insertions, 5 deletions
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 02de58b360..733b190e59 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -72,9 +72,9 @@ JUNO_RESET_STATUS_PHY | \ JUNO_RESET_STATUS_RC) -void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, - unsigned long trsl_addr, int window_size, - int trsl_param) +static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, + unsigned long trsl_addr, int window_size, + int trsl_param) { /* X3PCI_ATR_SRC_ADDR_LOW: - bit 0: enable entry, @@ -94,7 +94,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, ((u64)1) << window_size, trsl_param); } -void xr3pci_setup_atr(void) +static void xr3pci_setup_atr(void) { /* setup PCIe to CPU address translation tables */ unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0; @@ -141,7 +141,7 @@ void xr3pci_setup_atr(void) XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); } -void xr3pci_init(void) +static void xr3pci_init(void) { u32 val; int timeout = 200; @@ -193,5 +193,9 @@ void xr3pci_init(void) void vexpress64_pcie_init(void) { + /* Initialise and configure the PCIe host bridge. */ xr3pci_init(); + + /* Register the now ECAM complaint PCIe host controller with U-Boot. */ + pci_init(); } diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index fbfa7a18f1..5932a4a0c7 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -152,11 +152,13 @@ void reset_cpu(ulong addr) int board_eth_init(bd_t *bis) { int rc = 0; +#ifndef CONFIG_DM_ETH #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif #ifdef CONFIG_SMC911X rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif +#endif return rc; } |