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| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2019-03-12 17:50:23 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-06-24 14:07:58 +0300 |
| commit | ca0c0e07adf3c3baf3851fc17490a0160398c834 (patch) | |
| tree | 2814d566c027c0a829e1992d03c68452b626cbb5 /board | |
| parent | c64afba2fb483d416ad5da9dfe3f1f156ccf2366 (diff) | |
| download | u-boot-ca0c0e07adf3c3baf3851fc17490a0160398c834.tar.xz | |
fpga: zynqpl: Flush dcache only for non-bitstream data
In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board')
0 files changed, 0 insertions, 0 deletions