diff options
author | Valentin Longchamp <valentin.longchamp@keymile.com> | 2013-10-18 13:47:24 +0400 |
---|---|---|
committer | York Sun <yorksun@freescale.com> | 2013-10-24 20:36:26 +0400 |
commit | 877bfe37dc00b0ae59f37742954a62bce3fdf3a0 (patch) | |
tree | f0ea1e47a471cd0e255f55090d63c7286347dc8f /board | |
parent | 935b402eaec0f78ffdafd614aa8176a777d8b6d9 (diff) | |
download | u-boot-877bfe37dc00b0ae59f37742954a62bce3fdf3a0.tar.xz |
mpc85xx: introduce the kmp204x reference design support
This patch introduces the support for Keymile's kmp204x reference
design. This design is based on Freescale's P2040/P2041 SoC.
The peripherals used by this design are:
- DDR3 RAM with SPD support
- SPI NOR Flash as boot medium
- NAND Flash
- 2 PCIe busses (hosts 1 and 3)
- 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5)
- 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt
FPGA
- 2 HW I2C busses
- last but not least, the mandatory serial port
The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb
support and was changed according to our design (that means essentially
removing what is not present on the designs and a few adaptations).
There is currently only one prototype board that is based on this design
and this patch also introduces it. The board is called kmlion1.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
kmp204x: update the ENV #define
The comments had to be refined as well as the total size
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix ddr.c]
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/keymile/kmp204x/Makefile | 48 | ||||
-rw-r--r-- | board/keymile/kmp204x/ddr.c | 64 | ||||
-rw-r--r-- | board/keymile/kmp204x/eth.c | 71 | ||||
-rw-r--r-- | board/keymile/kmp204x/kmp204x.c | 258 | ||||
-rw-r--r-- | board/keymile/kmp204x/kmp204x.h | 15 | ||||
-rw-r--r-- | board/keymile/kmp204x/law.c | 40 | ||||
-rw-r--r-- | board/keymile/kmp204x/pbi.cfg | 35 | ||||
-rw-r--r-- | board/keymile/kmp204x/pci.c | 35 | ||||
-rw-r--r-- | board/keymile/kmp204x/rcw_kmp204x.cfg | 11 | ||||
-rw-r--r-- | board/keymile/kmp204x/tlb.c | 110 |
10 files changed, 687 insertions, 0 deletions
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile new file mode 100644 index 0000000000..35d17ce9f5 --- /dev/null +++ b/board/keymile/kmp204x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ddr.o eth.o tlb.o pci.o law.o \ + ../common/common.o ../common/ivm.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c new file mode 100644 index 0000000000..bd425aab1a --- /dev/null +++ b/board/keymile/kmp204x/ddr.c @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + + /* automatic calibration for nb of cycles between read and DQS pre */ + popts->cpo_override = 0xFF; + + /* 1/2 clk delay between wr command and data strobe */ + popts->write_data_delay = 4; + /* clk lauched 1/2 applied cylcle after address command */ + popts->clk_adjust = 4; + /* 1T timing: command/address held for only 1 cycle */ + popts->twot_en = 0; + + /* we have only one module, half str should be OK */ + popts->half_strength_driver_enable = 1; + + /* wrlvl values overriden as recommended by ddr init func */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x6; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing with SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c new file mode 100644 index 0000000000..a0731055a2 --- /dev/null +++ b/board/keymile/kmp204x/eth.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <phy.h> + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + + printf("Initializing Fman\n"); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + /* DTESC1/2 don't have a PHY, they are temporarily disabled + * so that u-boot doesn't try to unsuccessfuly enable them */ + fm_disable_port(FM1_DTSEC1); + fm_disable_port(FM1_DTSEC2); + + /* + * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf + * This is the debug interface, the only one used in u-boot + */ + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_mdio(FM1_DTSEC5, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + ret = cpu_eth_init(bis); + + /* reenable DTSEC1/2 for later (kernel) */ + fm_enable_port(FM1_DTSEC1); + fm_enable_port(FM1_DTSEC2); +#endif + + return ret; +} + +#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL) + +#define mv88E1118_PAGE_REG 22 + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) { + /* driver config is good */ + if (phydev->drv->config) + phydev->drv->config(phydev); + + /* but we still need to fix the LEDs */ + phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); + phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); + phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); + } + + return 0; +} +#endif diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c new file mode 100644 index 0000000000..f02642aece --- /dev/null +++ b/board/keymile/kmp204x/kmp204x.c @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * Copyright 2011,2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> + +#include "../common/common.h" +#include "kmp204x.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME); + + return 0; +} + +/* TODO: implement the I2C deblocking function */ +int i2c_make_abort(void) +{ + return 1; +} + +#define ZL30158_RST 8 +#define ZL30343_RST 9 + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ + setbits_be32(&gur->ddrclkdr, 0x001f000f); + + /* take the Zarlinks out of reset as soon as possible */ + qrio_prst(ZL30158_RST, false, false); + qrio_prst(ZL30343_RST, false, false); + + /* and set their reset to power-up only */ + qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); + qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); + + return 0; +} + +int board_early_init_r(void) +{ + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + set_liodns(); + setup_portals(); + + return 0; +} + +unsigned long get_board_sys_clk(unsigned long dummy) +{ + return 66666666; +} + +#define WDMASK_OFF 0x16 + +static void qrio_wdmask(u8 bit, bool wden) +{ + u16 wdmask; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + wdmask = in_be16(qrio_base + WDMASK_OFF); + + if (wden) + wdmask |= (1 << bit); + else + wdmask &= ~(1 << bit); + + out_be16(qrio_base + WDMASK_OFF, wdmask); +} + +#define PRST_OFF 0x1a + +void qrio_prst(u8 bit, bool en, bool wden) +{ + u16 prst; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + qrio_wdmask(bit, wden); + + prst = in_be16(qrio_base + PRST_OFF); + + if (en) + prst &= ~(1 << bit); + else + prst |= (1 << bit); + + out_be16(qrio_base + PRST_OFF, prst); +} + +#define PRSTCFG_OFF 0x1c + +void qrio_prstcfg(u8 bit, u8 mode) +{ + u32 prstcfg; + u8 i; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + prstcfg = in_be32(qrio_base + PRSTCFG_OFF); + + for (i = 0; i < 2; i++) { + if (mode & (1<<i)) + set_bit(2*bit+i, &prstcfg); + else + clear_bit(2*bit+i, &prstcfg); + } + + out_be32(qrio_base + PRSTCFG_OFF, prstcfg); +} + + +#define BOOTCOUNT_OFF 0x12 + +void bootcount_store(ulong counter) +{ + u8 val; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + val = (counter <= 255) ? (u8)counter : 255; + out_8(qrio_base + BOOTCOUNT_OFF, val); +} + +ulong bootcount_load(void) +{ + u8 val; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + val = in_8(qrio_base + BOOTCOUNT_OFF); + return val; +} + +#define NUM_SRDS_BANKS 2 +#define PHY_RST 15 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100, + SRDS_PLLCR0_RFCK_SEL_125}; + unsigned int i; + + /* check SERDES reference clocks */ + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 actual = in_be32(®s->bank[i].pllcr0); + actual &= SRDS_PLLCR0_RFCK_SEL_MASK; + if (actual != expected[i]) { + printf("Warning: SERDES bank %u expects reference \ + clock %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected[i]), + serdes_clock_to_string(actual)); + } + } + + /* take the mgmt eth phy out of reset */ + qrio_prst(PHY_RST, false, false); + + return 0; +} + +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + ivm_read_eeprom(); + return 0; +} +#endif + +#if defined(CONFIG_LAST_STAGE_INIT) +int last_stage_init(void) +{ + set_km_env(); + return 0; +} +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_fman_mac_addresses(void *blob) +{ + int node, i, ret; + char *tmp, *end; + unsigned char mac_addr[6]; + + /* get the mac addr from env */ + tmp = getenv("ethaddr"); + if (!tmp) { + printf("ethaddr env variable not defined\n"); + return; + } + for (i = 0; i < 6; i++) { + mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* find the correct fdt ethernet path and correct it */ + node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return; + } + ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return; + } +} +#endif + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_fman_mac_addresses(blob); +#endif +} diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h new file mode 100644 index 0000000000..b6ba672413 --- /dev/null +++ b/board/keymile/kmp204x/kmp204x.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 +#define PRSTCFG_POWUP_UNIT_RST 0x1 +#define PRSTCFG_POWUP_RST 0x3 + +void qrio_prst(u8 bit, bool en, bool wden); +void qrio_prstcfg(u8 bit, u8 mode); + +void pci_of_setup(void *blob, bd_t *bd); diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c new file mode 100644 index 0000000000..75d69e8b48 --- /dev/null +++ b/board/keymile/kmp204x/law.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), +#endif + SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS + SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS + SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg new file mode 100644 index 0000000000..f38dcf9c8c --- /dev/null +++ b/board/keymile/kmp204x/pbi.cfg @@ -0,0 +1,35 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 27170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c new file mode 100644 index 0000000000..ec20c8afb4 --- /dev/null +++ b/board/keymile/kmp204x/pci.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +#include "kmp204x.h" + +#define PCIE_SW_RST 14 +#define HOOPER_SW_RST 12 + +void pci_init_board(void) +{ + qrio_prst(PCIE_SW_RST, false, false); + qrio_prst(HOOPER_SW_RST, false, false); + /* Hooper is not direcly PCIe capable */ + mdelay(50); + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg new file mode 100644 index 0000000000..f2b7fe3d42 --- /dev/null +++ b/board/keymile/kmp204x/rcw_kmp204x.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for kmp204x boards +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +14600000 00000000 28200000 00000000 +148E70CF CFC02000 58000000 41000000 +00000000 00000000 00000000 F4428002 +00000000 00000000 00000000 00000000 diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c new file mode 100644 index 0000000000..d03ca802a4 --- /dev/null +++ b/board/keymile/kmp204x/tlb.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp <valentin.longchamp@keymile.com> + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + /* TLB 1 */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + /* QRIO */ + SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_64K, 1), + /* *I*G* - PCI1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + /* *I*G* - PCI3 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_512M, 1), + /* *I*G* - PCI1&3 I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_128K, 1), +#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS + /* LBAPP1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), +#endif +#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS + /* LBAPP2 */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), +#endif + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_32K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); |