diff options
author | Jagan Teki <jagan@amarulasolutions.com> | 2020-07-08 21:52:35 +0300 |
---|---|---|
committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-07-09 18:28:06 +0300 |
commit | f247354708ec93e995cf61901adc6d728762b196 (patch) | |
tree | 3db0dd18b735beabd141b6f17f6f13d14cb285bb /board | |
parent | 5d1281296fc26144c57fd26ba4e2fb97419f437a (diff) | |
download | u-boot-f247354708ec93e995cf61901adc6d728762b196.tar.xz |
arm: Remove mx31pdk board
DM, OF_CONTROL, DM_SPI and other driver model migration
deadlines are expired for this board.
Remove it.
Acked-by: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/freescale/mx31pdk/Kconfig | 15 | ||||
-rw-r--r-- | board/freescale/mx31pdk/MAINTAINERS | 6 | ||||
-rw-r--r-- | board/freescale/mx31pdk/Makefile | 11 | ||||
-rw-r--r-- | board/freescale/mx31pdk/lowlevel_init.S | 76 | ||||
-rw-r--r-- | board/freescale/mx31pdk/mx31pdk.c | 119 |
5 files changed, 0 insertions, 227 deletions
diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig deleted file mode 100644 index 055545c930..0000000000 --- a/board/freescale/mx31pdk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX31PDK - -config SYS_BOARD - default "mx31pdk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "mx31pdk" - -endif diff --git a/board/freescale/mx31pdk/MAINTAINERS b/board/freescale/mx31pdk/MAINTAINERS deleted file mode 100644 index ec2a32063b..0000000000 --- a/board/freescale/mx31pdk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX31PDK BOARD -M: Magnus Lilja <lilja.magnus@gmail.com> -S: Maintained -F: board/freescale/mx31pdk/ -F: include/configs/mx31pdk.h -F: configs/mx31pdk_defconfig diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile deleted file mode 100644 index 7edc60f0d2..0000000000 --- a/board/freescale/mx31pdk/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifdef CONFIG_SPL_BUILD -obj-y += lowlevel_init.o -endif -obj-y += mx31pdk.o diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S deleted file mode 100644 index d78459faf6..0000000000 --- a/board/freescale/mx31pdk/lowlevel_init.S +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> - */ - -#include <config.h> -#include <asm/arch/imx-regs.h> -#include <asm/macro.h> - -.globl lowlevel_init -lowlevel_init: - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - - write32 IPU_CONF, IPU_CONF_DI_EN - write32 CCM_CCMR, CCM_CCMR_SETUP - - wait_timer 0x40000 - - write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE - write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS - - /* Set up clock to 532MHz */ - write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ - write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ - - write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - - /* Set up MX31 DDR pins */ - write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 - write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 - write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 - write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 - write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 - write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 - write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 - write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 - write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 - write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 - write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 - write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 - write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 - write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 - write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 - write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 - write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 - write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 - write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 - write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 - write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 - write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 - write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 - write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 - write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 - write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 - write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 - - /* Set up MX31 DDR Memory Controller */ - write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP - write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP - - /* Perform DDR init sequence */ - write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE - write32 CSD0_BASE | 0x0f00, 0x12344321 - write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH - write32 CSD0_BASE, 0x12344321 - write32 CSD0_BASE, 0x12344321 - write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG - write8 CSD0_BASE | 0x00000033, 0xda - write8 CSD0_BASE | 0x01000000, 0xff - write32 WEIM_ESDCTL0, ESDCTL_RW - write32 CSD0_BASE, 0xDEADBEEF - write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL - - mov pc, lr diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c deleted file mode 100644 index 06fe51db71..0000000000 --- a/board/freescale/mx31pdk/mx31pdk.c +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - - -#include <common.h> -#include <init.h> -#include <net.h> -#include <netdev.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <watchdog.h> -#include <power/pmic.h> -#include <fsl_pmic.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong bootflag) -{ - /* - * copy ourselves from where we are running to where we were - * linked at. Use ulong pointers as all addresses involved - * are 4-byte-aligned. - */ - ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; - asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); - asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); - asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); - asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); - for (dst = start_ptr; dst < end_ptr; dst++) - *dst = *(dst+(run_ptr-link_ptr)); - /* - * branch to nand_boot's link-time address. - */ - asm volatile("ldr pc, =nand_boot"); -} -#endif - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - /* CS5: CPLD incl. network controller */ - static const struct mxc_weimcs cs5 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(5, &cs5); - - /* Setup UART1 and SPI2 pins */ - mx31_uart1_hw_init(); - mx31_spi2_hw_init(); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_late_init(void) -{ - u32 val; - struct pmic *p; - int ret; - - ret = pmic_init(CONFIG_FSL_PMIC_BUS); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - /* Enable RTC battery */ - pmic_reg_read(p, REG_POWER_CTL0, &val); - pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); - pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); -#ifdef CONFIG_HW_WATCHDOG - hw_watchdog_init(); -#endif - return 0; -} - -int checkboard(void) -{ - printf("Board: MX31PDK\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} |