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author | Tien Fong Chee <tien.fong.chee@intel.com> | 2019-05-07 12:42:25 +0300 |
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committer | Marek Vasut <marex@denx.de> | 2019-05-10 23:48:10 +0300 |
commit | f78b505f81334bb7a49d5807e007790d336340c4 (patch) | |
tree | 659f5c280b9f2ee07032b5333df76fa36d6049b1 /board | |
parent | 5c2ae96b60ade14ea1f4afeb50e2a3de56493bcc (diff) | |
download | u-boot-f78b505f81334bb7a49d5807e007790d336340c4.tar.xz |
ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/altera/arria10-socdk/fit_spl_fpga.its | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000000..adae997213 --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + + fpga-core-1 { + description = "FPGA core bitstream"; + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph-1", "fpga-core-1"; + }; + }; +}; |