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| author | Simon Glass <sjg@chromium.org> | 2019-12-07 07:42:51 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 06:44:24 +0300 |
| commit | e556d3d630d31fd966eb676fbe43a90bf06e6d29 (patch) | |
| tree | b9d51c00d5f12c69df85b93a2dbbf40a988b8689 /configs/chromebook_samus_tpl_defconfig | |
| parent | 4806fcea1a4b0143fc57932bc5cbdffdf8afca4e (diff) | |
| download | u-boot-e556d3d630d31fd966eb676fbe43a90bf06e6d29.tar.xz | |
x86: Enable pinctrl in SPL and TPL
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'configs/chromebook_samus_tpl_defconfig')
| -rw-r--r-- | configs/chromebook_samus_tpl_defconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 74b7e9a207..403b754ce9 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -72,6 +72,8 @@ CONFIG_SYS_I2C_DW=y CONFIG_TPL_MISC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y +# CONFIG_SPL_PINCTRL is not set +# CONFIG_TPL_PINCTRL is not set CONFIG_SYS_NS16550=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y |