diff options
| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-02-26 12:44:09 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-03-07 01:05:40 +0300 |
| commit | 6782b81588c204fccc2178d269d2d978851b123a (patch) | |
| tree | ef6c1d10f07ffbfe04c2d8520f4563cc2257cd81 /configs/gazerbeam_defconfig | |
| parent | e352e1061f4c9a8adb70b6ff819890c42e5b3ef7 (diff) | |
| download | u-boot-6782b81588c204fccc2178d269d2d978851b123a.tar.xz | |
powerpc, mpc83xx: Remove CONFIG_ELBC_BRx_ORx
Commit fe7d654d04 ("mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to
Kconfig") converted CONFIG_SYS_{BRx/ORx}_PRELIM to Kconfig by
implementing a fine-grained selection of every bit in Kconfig.
But commit c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to
Kconfig") reworked it so that you now just have to provide the raw
value of each register in Kconfig. However, all fine-grained
Kconfig items remained allthough they are not used anymore.
Remove them all.
Fixes: c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'configs/gazerbeam_defconfig')
| -rw-r--r-- | configs/gazerbeam_defconfig | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 63051af411..63488da30a 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -67,31 +67,6 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xE0700000 CONFIG_LBLAW2_NAME="FPGA1" CONFIG_LBLAW2_LENGTH_1_MBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="FPGA0" -CONFIG_BR1_OR1_BASE=0xE0600000 -CONFIG_BR1_PORTSIZE_16BIT=y -CONFIG_OR1_AM_1_MBYTES=y -CONFIG_OR1_SCY_5=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="FPGA1" -CONFIG_BR2_OR2_BASE=0xE0700000 -CONFIG_BR2_PORTSIZE_16BIT=y -CONFIG_OR2_AM_1_MBYTES=y -CONFIG_OR2_SCY_5=y -CONFIG_OR2_CSNT_EARLIER=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y |