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| author | Jianlong Huang <jianlong.huang@starfivetech.com> | 2022-06-30 13:35:56 +0300 |
|---|---|---|
| committer | Jianlong Huang <jianlong.huang@starfivetech.com> | 2022-11-03 11:22:14 +0300 |
| commit | ad9e1dc0ba91125117eb8d2a8474048c9632c530 (patch) | |
| tree | 344671c7926baf8404e6f5c9038e1959a2dcbf31 /configs/starfive_visionfive2_defconfig | |
| parent | b8632bd416725e28894ef5bb8b4ede92d4f5bfd4 (diff) | |
| download | u-boot-ad9e1dc0ba91125117eb8d2a8474048c9632c530.tar.xz | |
board: starfive: Support visionfive2
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Diffstat (limited to 'configs/starfive_visionfive2_defconfig')
| -rw-r--r-- | configs/starfive_visionfive2_defconfig | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig new file mode 100644 index 0000000000..48f8936833 --- /dev/null +++ b/configs/starfive_visionfive2_defconfig @@ -0,0 +1,87 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="starfive_visionfive2" +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_BUILD_TARGET="" +CONFIG_TARGET_STARFIVE_VISIONFIVE2=y +CONFIG_NR_CPUS=5 +CONFIG_FPGA_GMAC_SPEED_AUTO=y +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +CONFIG_SHOW_REGS=y +CONFIG_FIT=y +CONFIG_SPL_FIT_SOURCE="jh7110-uboot-fit-image.its" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_SPI_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_LOG_MAX_LEVEL=4 +CONFIG_SPL_LOG=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="StarFive # " +CONFIG_CMD_CONFIG=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_MISC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_LOG=y +CONFIG_OF_EMBED=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_JH7110=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +# CONFIG_PHY_MSCC is not set +CONFIG_PHY_YUTAI=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_STARFIVE=y +CONFIG_RGMII=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_SPL_STARFIVE_DDR=y +CONFIG_DM_RESET=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT_OVERLAY=y |