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| author | Tom Rini <trini@konsulko.com> | 2020-09-25 16:04:01 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-25 16:04:01 +0300 |
| commit | 0ac83d080a0044cd0d8f782ba12f02cf969d3004 (patch) | |
| tree | ca5c2351113ba9b56d59e241a8857c7e6e8f5604 /configs | |
| parent | 67ece26d8b5d4bfa4fda8c456261c465d0815d7d (diff) | |
| parent | 8c180d669a0f4a8eb70bde8c74c73cef45993f67 (diff) | |
| download | u-boot-0ac83d080a0044cd0d8f782ba12f02cf969d3004.tar.xz | |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Enhance the 'zboot' command to be more like 'bootm' with sub-commands
- The last series of ACPI core changes for programmatic generation of
ACPI tables
- Add all required ACPI tables for ApolloLake and enable ACPIGEN on
Chromebook Coral
- A feature minor enhancements to the 'hob' command
- Intel edison: Support for writing an xFSTK image via binman
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/chromebook_coral_defconfig | 13 | ||||
| -rw-r--r-- | configs/chromebook_link_defconfig | 2 |
2 files changed, 12 insertions, 3 deletions
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index e1d0749239..af0397ff1f 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x3d00 CONFIG_NR_DRAM_BANKS=8 CONFIG_SPL_DM_SPI=y CONFIG_SPL_TEXT_BASE=0xfef10000 +CONFIG_MAX_CPUS=8 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000 CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000 CONFIG_DEBUG_UART_BOARD_INIT=y @@ -14,10 +15,12 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_CORAL=y CONFIG_DEBUG_UART=y CONFIG_FSP_VERSION2=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_INTEL_CAR_CQOS=y -CONFIG_X86_OFFSET_U_BOOT=0xffe00000 +CONFIG_X86_OFFSET_U_BOOT=0xffd00000 CONFIG_X86_OFFSET_SPL=0xffe80000 +CONFIG_INTEL_GENERIC_WIFI=y CONFIG_BOOTSTAGE=y CONFIG_SPL_BOOTSTAGE=y CONFIG_TPL_BOOTSTAGE=y @@ -25,13 +28,14 @@ CONFIG_BOOTSTAGE_REPORT=y CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10 CONFIG_BOOTSTAGE_STASH=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200" +CONFIG_BOOTARGS="console=ttyS2,115200n8 cros_legacy loglevel=9 init=/sbin/init oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw noinitrd vt.global_cursor_default=0 add_efi_memmap boot=local noresume noswap i915.modeset=1 nmi_watchdog=panic,lapic disablevmx=off" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set +CONFIG_BLOBLIST_SIZE=0x30000 CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_HANDOFF=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y @@ -71,9 +75,12 @@ CONFIG_ENV_OVERWRITE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_INTEL_ACPIGEN=y CONFIG_CPU=y +CONFIG_BOARD=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y CONFIG_TPL_MISC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y @@ -85,7 +92,9 @@ CONFIG_PINCTRL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SOUND=y +CONFIG_SOUND_DA7219=y CONFIG_SOUND_I8254=y +CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_RT5677=y CONFIG_SPI=y CONFIG_ICH_SPI=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 82485a5a3f..c59a7f3c99 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_TEXT_BASE=0xFFEF0000 CONFIG_SYS_MALLOC_F_LEN=0x2400 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 |