diff options
author | Wolfgang Denk <wd@denx.de> | 2010-04-01 13:28:32 +0400 |
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committer | Wolfgang Denk <wd@denx.de> | 2010-04-01 13:28:32 +0400 |
commit | ffa37fc98d71ef930bccd4e9eed37f6ce6b4d6af (patch) | |
tree | 206908754219b5cc6e9f03518d34fb95a247bef9 /cpu | |
parent | ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55 (diff) | |
parent | fd03ea89641d6f6ade6d1a8580c1bb9f52b8542c (diff) | |
download | u-boot-ffa37fc98d71ef930bccd4e9eed37f6ce6b4d6af.tar.xz |
Merge branch 'next'
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/mcf5227x/cpu_init.c | 16 | ||||
-rw-r--r-- | cpu/mcf5227x/start.S | 100 | ||||
-rw-r--r-- | cpu/mcf523x/cpu_init.c | 26 | ||||
-rw-r--r-- | cpu/mcf523x/start.S | 75 | ||||
-rw-r--r-- | cpu/mcf52x2/cpu_init.c | 86 | ||||
-rw-r--r-- | cpu/mcf52x2/start.S | 176 | ||||
-rw-r--r-- | cpu/mcf532x/config.mk | 12 | ||||
-rw-r--r-- | cpu/mcf532x/cpu_init.c | 39 | ||||
-rw-r--r-- | cpu/mcf532x/speed.c | 2 | ||||
-rw-r--r-- | cpu/mcf532x/start.S | 72 | ||||
-rw-r--r-- | cpu/mcf5445x/cpu_init.c | 45 | ||||
-rw-r--r-- | cpu/mcf5445x/start.S | 123 | ||||
-rw-r--r-- | cpu/mcf547x_8x/cpu_init.c | 4 | ||||
-rw-r--r-- | cpu/mcf547x_8x/start.S | 83 | ||||
-rw-r--r-- | cpu/mpc5xxx/Makefile | 2 | ||||
-rw-r--r-- | cpu/mpc5xxx/cpu.c | 7 | ||||
-rw-r--r-- | cpu/mpc5xxx/cpu_init.c | 35 | ||||
-rw-r--r-- | cpu/mpc5xxx/firmware_sc_task.impl.S | 364 | ||||
-rw-r--r-- | cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S | 4 | ||||
-rw-r--r-- | cpu/mpc5xxx/pci_mpc5200.c | 4 | ||||
-rw-r--r-- | cpu/mpc5xxx/serial.c | 17 | ||||
-rw-r--r-- | cpu/mpc5xxx/start.S | 8 | ||||
-rw-r--r-- | cpu/mpc5xxx/usb_ohci.c | 7 | ||||
-rw-r--r-- | cpu/mpc5xxx/usb_ohci.h | 5 |
24 files changed, 200 insertions, 1112 deletions
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c index e160ee1aff..beb78f5839 100644 --- a/cpu/mcf5227x/cpu_init.c +++ b/cpu/mcf5227x/cpu_init.c @@ -125,27 +125,27 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->par_uart &= - (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); + (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK); gpio->par_uart |= (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: gpio->par_uart &= - (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK); + (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK); gpio->par_uart |= (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); break; case 2: gpio->par_dspi &= - (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK); + (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK); gpio->par_dspi = (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); break; @@ -175,11 +175,11 @@ int cfspi_claim_bus(uint bus, uint cs) switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK; + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK; gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; break; } @@ -199,7 +199,7 @@ void cfspi_release_bus(uint bus, uint cs) gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; break; } } diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index 0c9c89c402..30428f15d8 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - #define _START _start #define _FAULT _fault @@ -378,21 +374,19 @@ _start: movec %d0, %RAMBAR1 #endif + /* invalidate and disable cache */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + /* initialize general use internal ram */ move.l #0, %d0 move.l #(ICACHE_STATUS), %a1 /* icache */ move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ @@ -510,84 +504,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR0 - - move.l #0x81600610, %d0 /* Enable cache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01F00000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600610, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #0x81300610, %d0 - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0x81600610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #0x81100610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c index 3c04fd4134..0f299f0c3c 100644 --- a/cpu/mcf523x/cpu_init.c +++ b/cpu/mcf523x/cpu_init.c @@ -130,21 +130,32 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); break; case 1: - gpio->par_uart = - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + gpio->par_uart &= + ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); break; case 2: - gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + gpio->feci2c |= + (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); +#endif break; } } @@ -156,7 +167,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear) if (setclear) { gpio->par_feci2c |= - (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + (GPIO_PAR_FECI2C_EMDC_FECEMDC | + GPIO_PAR_FECI2C_EMDIO_FECEMDIO); } else { gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S index d44da37ec7..20b50e7579 100644 --- a/cpu/mcf523x/start.S +++ b/cpu/mcf523x/start.S @@ -24,6 +24,7 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -135,7 +136,7 @@ _start: movec %d0, %RAMBAR1 /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ nop move.l #0, %d0 @@ -144,8 +145,8 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ move.l %d0, (%a1) move.l %d0, (%a2) @@ -265,74 +266,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - nop - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - rts - - .globl dcache_enable -dcache_enable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - /* No dcache, just a dummy function */ - .globl dcache_disable -dcache_disable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 7cea6558fd..170bbfc356 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -5,6 +5,8 @@ * MCF5282 additionals * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> + * (c) Copyright 2010 + * Arcturus Networks Inc. <www.arcturusnetworks.com> * * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) @@ -133,36 +135,36 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart &= GPIO_PAR_UART0_MASK; + gpio->par_uart &= GPIO_PAR_UART0_UNMASK; gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: - gpio->par_uart &= GPIO_PAR_UART0_MASK; + gpio->par_uart &= GPIO_PAR_UART0_UNMASK; gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO gpio->par_timer &= - (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK); + (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK); gpio->par_timer |= (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO gpio->par_feci2c &= - (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK); + (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK); gpio->par_feci2c |= (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO gpio->par_feci2c &= - (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); + (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); gpio->par_feci2c |= (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); #endif @@ -182,8 +184,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear) GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; } else { gpio->par_fec &= - (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK; + (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK; } return 0; } @@ -245,15 +247,19 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { + volatile u32 *par = (u32 *) MMAP_PAR; + /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - break; + switch (port) { case 1: + *par &= 0xFFE7FFFF; + *par |= 0x00180000; break; case 2: + *par &= 0xFFFFFFFC; + *par &= 0x00000003; break; } } @@ -289,21 +295,26 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { + u16 temp; + /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | - MCF_GPIO_PAR_UART_U0RXD); + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; + temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); break; case 1: - mbar_writeShort(MCF_GPIO_PAR_UART, - MCF_GPIO_PAR_UART_U1RXD_UART1 | - MCF_GPIO_PAR_UART_U1TXD_UART1); + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; + temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); break; case 2: - mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); + temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; + temp |= (0x3000); + mbar_writeShort(MCF_GPIO_PAR_UART, temp); break; } } @@ -407,12 +418,12 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); @@ -485,19 +496,22 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: + gpio->par_uart &= ~UART0_ENABLE_MASK; gpio->par_uart |= UART0_ENABLE_MASK; break; case 1: + gpio->par_uart &= ~UART1_ENABLE_MASK; gpio->par_uart |= UART1_ENABLE_MASK; break; case 2: + gpio->par_uart &= ~UART2_ENABLE_MASK; gpio->par_uart |= UART2_ENABLE_MASK; break; } @@ -582,6 +596,12 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTCPAR MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; #endif +#if defined(CONFIG_SYS_PORTTC) + MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; +#endif +#if defined(CONFIG_SYS_DDRTC) + MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; +#endif #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif @@ -589,6 +609,9 @@ void cpu_init_f(void) MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; #endif +#if defined(CONFIG_SYS_DDRD) + MCFGPIO_DDRD = CONFIG_SYS_DDRD; +#endif #ifdef CONFIG_SYS_DDRUA MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; #endif @@ -610,10 +633,10 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: MCFGPIO_PUAPAR &= 0xFc; MCFGPIO_PUAPAR |= 0x03; @@ -718,14 +741,7 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { - /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { - case 0: - break; - case 1: - break; - } } #endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 0dd4de5160..9ef206aa0f 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -24,12 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif - #define _START _start #define _FAULT _fault @@ -201,6 +201,13 @@ _after_flashbar_copy: movec %d0, %RAMBAR1 #endif + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- @@ -283,23 +290,6 @@ clear_bss: cmp.l %a2, %a1 bne 7b -#if defined(CONFIG_M5281) || defined(CONFIG_M5282) - /* patch the 3 accesspoints to 3 ichache_state */ - /* quick and dirty */ - - move.l %a0,%d1 - add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1 - move.l %a0,%a1 - add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) - move.l %a0,%a1 - add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) - move.l %a0,%a1 - add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %d1,(%a1) -#endif - /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 @@ -336,156 +326,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ -#ifdef CONFIG_M5208 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - -#ifdef CONFIG_M5271 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - -#ifdef CONFIG_M5272 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#if defined(CONFIG_M5275) -/* - * Instruction cache only - */ - .globl icache_enable -icache_enable: - move.l #0x01400000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup SDRAM caching */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0x00000000, %d0 /* No other caching */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#ifdef CONFIG_M5282 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 -icache_state_access_1: - move.l %d0, icache_state - rts -#endif - -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) - .globl icache_enable -icache_enable: - /* - * Note: The 5249 Documentation doesn't give a bit position for CINV! - * From the 5272 and the 5307 documentation, I have deduced that it is - * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy - */ - move.l #0x01000000, %d0 /* Invalidate whole cache */ - move.c %d0,%CACR - move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */ - move.c %d0, %ACR0 - move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */ - move.c %d0, %ACR1 - move.l #0x90000200, %d0 /* Set cache enable cmd */ - move.c %d0,%CACR - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - movec %d0, %ACR1 /* Enable cache */ - moveq #0, %d0 -icache_state_access_2: - move.l %d0, icache_state - rts - - .globl icache_status -icache_status: -icache_state_access_3: - move.l #(icache_state), %a0 - move.l (%a0), %d0 - rts - - .data -icache_state: - .long 0 /* cache is diabled on inirialization */ - - .globl dcache_enable -dcache_enable: - /* dummy function */ - rts - - .globl dcache_disable -dcache_disable: - /* dummy function */ - rts - - .globl dcache_status -dcache_status: - /* dummy function */ - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk index 0cb90ac4e2..b783444ae8 100644 --- a/cpu/mcf532x/config.mk +++ b/cpu/mcf532x/config.mk @@ -24,8 +24,20 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data + +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg)) +is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg)) + ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) + +ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) +PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC +endif +ifneq (,$(findstring CONFIG_MCF532x,$(is532x))) PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC +endif + else PLATFORM_CPPFLAGS += -m5307 -fPIC endif diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 4f1695cef8..6f551b60c9 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -133,24 +133,26 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: #ifdef CONFIG_SYS_UART1_ALT1_GPIO gpio->par_simp1h &= - ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK); + ~(GPIO_PAR_SIMP1H_DATA1_UNMASK | + GPIO_PAR_SIMP1H_VEN1_UNMASK); gpio->par_simp1h |= (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) gpio->par_ssih &= - ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK); + ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK); gpio->par_ssih |= (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); #endif @@ -160,12 +162,12 @@ void uart_port_conf(void) gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) gpio->par_dspih &= - ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK); + ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK); gpio->par_dspih |= (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); + ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); gpio->par_feci2c |= (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); #endif @@ -195,11 +197,11 @@ int fecpin_setclear(struct eth_device *dev, int setclear) if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { gpio->par_fec &= ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK; + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK; } else { gpio->par_fec &= ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK; + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK; } } return 0; @@ -297,22 +299,33 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); break; case 1: - gpio->par_uart = + gpio->par_uart &= + ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + gpio->par_uart |= (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); break; case 2: +#ifdef CONFIG_SYS_UART2_ALT1_GPIO gpio->par_timer &= 0x0F; gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_feci2c &= 0xFF00; + gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); +#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) + gpio->par_ssi &= 0xF0FF; + gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); +#endif break; } } diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index 67f08c7602..5a29e2567a 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -229,7 +229,7 @@ int clock_pll(int fsys, int flags) PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | PLL_PDR_OUTDIV4(USBDIV - 1); - pll->pcr &= PLL_PCR_FBDIV_MASK; + pll->pcr &= PLL_PCR_FBDIV_UNMASK; pll->pcr |= PLL_PCR_FBDIV(mfd - 1); #endif #ifdef CONFIG_MCF532x diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 5b134aa47c..a80b0a9946 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -27,6 +27,7 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -142,7 +143,7 @@ _start: movec %d0, %RAMBAR1 /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ + move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -158,8 +159,8 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ move.l %d0, (%a1) move.l %d0, (%a2) @@ -279,71 +280,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0 - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x81000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - /* No dcache, just a dummy function */ - .globl dcache_disable -dcache_disable: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ - .globl version_string version_string: .ascii U_BOOT_VERSION diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 48b37dfe7d..8d51d35d68 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/processor.h> #include <asm/rtc.h> #if defined(CONFIG_CMD_NET) @@ -105,6 +106,14 @@ void cpu_init_f(void) fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif + /* + * now the flash base address is no longer at 0 (Newer ColdFire family + * boot at address 0 instead of 0xFFnn_nnnn). The vector table must + * also move to the new location. + */ + if (CONFIG_SYS_CS0_BASE != 0) + setvbr(CONFIG_SYS_CS0_BASE); + #ifdef CONFIG_FSL_I2C gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; #endif @@ -128,19 +137,43 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: - gpio->par_uart = + gpio->par_uart &= + ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + gpio->par_uart |= (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: - gpio->par_uart = +#ifdef CONFIG_SYS_UART1_PRI_GPIO + gpio->par_uart &= + ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + gpio->par_uart |= (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); +#elif defined(CONFIG_SYS_UART1_ALT1_GPIO) + gpio->par_ssi &= + (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK); + gpio->par_ssi |= + (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); +#endif + break; + case 2: +#if defined(CONFIG_SYS_UART2_ALT1_GPIO) + gpio->par_timer &= + (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK); + gpio->par_timer |= + (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); +#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) + gpio->par_timer &= + (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK); + gpio->par_timer |= + (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); +#endif break; } } @@ -164,9 +197,9 @@ int fecpin_setclear(struct eth_device *dev, int setclear) ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK; else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK; } return 0; } diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index d2d4439151..738e4a7110 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) - #define _START _start #define _FAULT _fault @@ -160,15 +156,13 @@ asm_dram_init: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -411,15 +405,13 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -544,107 +536,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */ - movec %d0, %ACR2 - - move.l #0x04088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0xFFF77BFF, %d0 - or.l #0x00040100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x01040100, %d0 - movec %d0, %CACR /* Invalidate dcache */ - - move.l #0x80088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - and.l #0x7FFFFFFF, %d0 - or.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable dcache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x81088020, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c index 96a3132b78..60c91267a7 100644 --- a/cpu/mcf547x_8x/cpu_init.c +++ b/cpu/mcf547x_8x/cpu_init.c @@ -113,13 +113,13 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S index 94ef14bf3d..84118629e2 100644 --- a/cpu/mcf547x_8x/start.S +++ b/cpu/mcf547x_8x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - #define _START _start #define _FAULT _fault @@ -158,10 +154,8 @@ _start: move.l #0, %d0 move.l #(ICACHE_STATUS), %a1 /* icache */ move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ @@ -279,81 +273,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR2 /* Enable cache */ - - move.l #0x020C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x000C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_invalid -icache_invalid: - move.l #0x000C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl dcache_enable -dcache_enable: - bsr icache_disable - - move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 - movec %d0, %ACR0 /* Enable cache */ - - move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0xA30C8100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile index 06fdbcfb72..0ee0611550 100644 --- a/cpu/mpc5xxx/Makefile +++ b/cpu/mpc5xxx/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o +SOBJS = io.o firmware_sc_task_bestcomm.impl.o COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index edfb8282b7..b20234d32e 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -50,16 +50,10 @@ int checkcpu (void) { ulong clock = gd->cpu_clk; char buf[32]; -#ifndef CONFIG_MGT5100 uint svr, pvr; -#endif puts ("CPU: "); -#ifdef CONFIG_MGT5100 - puts (CPU_ID_STR); - printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID); -#else svr = get_svr(); pvr = get_pvr(); @@ -77,7 +71,6 @@ int checkcpu (void) printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), PVR_MAJ(pvr), PVR_MIN(pvr)); -#endif printf (" at %s MHz\n", strmhz (buf, clock)); return 0; } diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index 560c9b311c..9daf3755ac 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -53,10 +53,6 @@ void cpu_init_f (void) (struct mpc5xxx_gpt *) MPC5XXX_GPT; #endif /* CONFIG_WATCHDOG */ unsigned long addecr = (1 << 25); /* Boot_CS */ - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) - addecr |= (1 << 22); /* SDRAM enable */ -#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -136,7 +132,6 @@ void cpu_init_f (void) out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG); #endif -#if defined(CONFIG_MPC5200) addecr |= 1; #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START)); @@ -164,14 +159,9 @@ void cpu_init_f (void) #if defined(CONFIG_SYS_CS_DEADCYCLE) out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE); #endif -#endif /* CONFIG_MPC5200 */ /* Enable chip selects */ -#if defined(CONFIG_MGT5100) - out_be32(&mm->addecr, addecr); -#elif defined(CONFIG_MPC5200) out_be32(&mm->ipbi_ws_ctrl, addecr); -#endif out_be32(&lpb->cs_ctrl, (1 << 24)); /* Setup pin multiplexing */ @@ -179,7 +169,6 @@ void cpu_init_f (void) out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); #endif -#if defined(CONFIG_MPC5200) /* enable timebase */ setbits_be32(&xlb->config, (1 << 13)); @@ -187,33 +176,29 @@ void cpu_init_f (void) setbits_be32(&xlb->config, (1 << 15)); out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d); -# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) +#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) /* Motorola reports IPB should better run at 133 MHz. */ -# if defined(CONFIG_MGT5100) - setbits_be32(&mm->addecr, 1); -# elif defined(CONFIG_MPC5200) setbits_be32(&mm->ipbi_ws_ctrl, 1); -# endif /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ addecr = in_be32(&cdm->cfg); addecr &= ~0x103; -# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) +# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ addecr |= 0x01; -# else +# else /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ addecr |= 0x02; -# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ +# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ out_be32(&cdm->cfg, addecr); -# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ +#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ /* Configure the XLB Arbiter */ out_be32(&xlb->master_pri_enable, 0xff); out_be32(&xlb->master_priority, 0x11111111); -# if defined(CONFIG_SYS_XLB_PIPELINING) +#if defined(CONFIG_SYS_XLB_PIPELINING) /* Enable piplining */ clrbits_be32(&xlb->config, (1 << 31)); -# endif +#endif #if defined(CONFIG_WATCHDOG) /* Charge the watchdog timer - prescaler = 64k, count = 64k*/ @@ -222,8 +207,6 @@ void cpu_init_f (void) reset_5xxx_watchdog(); #endif /* CONFIG_WATCHDOG */ - -#endif /* CONFIG_MPC5200 */ } /* @@ -235,11 +218,7 @@ int cpu_init_r (void) (struct mpc5xxx_intr *) MPC5XXX_ICTL; /* mask all interrupts */ -#if defined(CONFIG_MGT5100) - out_be32(&intr->per_mask, 0xfffffc00); -#elif defined(CONFIG_MPC5200) out_be32(&intr->per_mask, 0xffffff00); -#endif setbits_be32(&intr->main_mask, 0x0001ffff); clrbits_be32(&intr->ctrl, 0x00000f00); /* route critical ints to normal ints */ diff --git a/cpu/mpc5xxx/firmware_sc_task.impl.S b/cpu/mpc5xxx/firmware_sc_task.impl.S deleted file mode 100644 index b668ee5cf8..0000000000 --- a/cpu/mpc5xxx/firmware_sc_task.impl.S +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MGT5100 CPU. - */ - -#include <config.h> - -#if defined(CONFIG_MGT5100) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0004800 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0004800 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.align 8 -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 256, 0x0 - - -.align 8 -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 256, 0x0 - -#endif /* CONFIG_MGT5100 */ diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S index d140c7e989..00c23121ac 100644 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -6,8 +6,6 @@ #include <config.h> -#if defined(CONFIG_MPC5200) - /* sas/sccg, gas target */ .section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ .section smartdmaTaskTable,"aw",@progbits /* Task tables */ @@ -359,5 +357,3 @@ scEthernetRecv_CSave: /* Task 0 context save space */ .globl scEthernetXmit_CSave scEthernetXmit_CSave: /* Task 1 context save space */ .space 128, 0x0 - -#endif /* CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c index 225738a073..8268f8afe1 100644 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -23,7 +23,7 @@ #include <common.h> -#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) +#if defined(CONFIG_PCI) #include <asm/processor.h> #include <asm/io.h> @@ -184,4 +184,4 @@ void pci_mpc5xxx_init (struct pci_controller *hose) hose->last_busno = pci_hose_scan(hose); } -#endif /* CONFIG_PCI && CONFIG_MPC5200 */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index a8a384aa58..66759887c6 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -50,8 +50,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PSC_BASE MPC5XXX_PSC2 #elif CONFIG_PSC_CONSOLE == 3 #define PSC_BASE MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3 #elif CONFIG_PSC_CONSOLE == 4 #define PSC_BASE MPC5XXX_PSC4 #elif CONFIG_PSC_CONSOLE == 5 @@ -73,8 +71,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PSC_BASE2 MPC5XXX_PSC2 #elif CONFIG_PSC_CONSOLE2 == 3 #define PSC_BASE2 MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3 #elif CONFIG_PSC_CONSOLE2 == 4 #define PSC_BASE2 MPC5XXX_PSC4 #elif CONFIG_PSC_CONSOLE2 == 5 @@ -104,23 +100,14 @@ int serial_init (void) psc->command = PSC_SEL_MODE_REG_1; /* select clock sources */ -#if defined(CONFIG_MGT5100) - psc->psc_clock_select = 0xdd00; - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) psc->psc_clock_select = 0; baseclk = (gd->ipb_clk + 16) / 32; -#endif /* switch to UART mode */ psc->sicr = 0; /* configure parity, bit length and so on */ -#if defined(CONFIG_MGT5100) - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#elif defined(CONFIG_MPC5200) psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#endif psc->mode = PSC_MODE_ONE_STOP; /* set up UART divisor */ @@ -246,11 +233,7 @@ void serial_setbrg(void) #endif unsigned long baseclk, div; -#if defined(CONFIG_MGT5100) - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) baseclk = (gd->ipb_clk + 16) / 32; -#endif /* set up UART divisor */ div = (baseclk + (gd->baudrate/2)) / gd->baudrate; diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index d499da5036..ba49944210 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -111,9 +111,6 @@ boot_warm: # if defined(CONFIG_SYS_RAMBOOT) # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT # endif /* CONFIG_SYS_RAMBOOT */ -# if defined(CONFIG_MGT5100) -# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100 -# endif /* CONFIG_MGT5100 */ lis r4, CONFIG_SYS_DEFAULT_MBAR@h lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l @@ -145,14 +142,9 @@ lowboot_reentry: #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) lis r3, CONFIG_SYS_MBAR@h ori r3, r3, CONFIG_SYS_MBAR@l -#if defined(CONFIG_MPC5200) /* MBAR is mirrored into the MBAR SPR */ mtspr MBAR,r3 rlwinm r3, r3, 16, 16, 31 -#endif -#if defined(CONFIG_MGT5100) - rlwinm r3, r3, 17, 15, 31 -#endif lis r4, CONFIG_SYS_DEFAULT_MBAR@h stw r3, 0(r4) #endif /* CONFIG_SYS_DEFAULT_MBAR */ diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c index 66a4af8d8e..7976e4df7d 100644 --- a/cpu/mpc5xxx/usb_ohci.c +++ b/cpu/mpc5xxx/usb_ohci.c @@ -76,13 +76,8 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#ifdef CONFIG_MPC5200 #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) -#else -#define ohci_cpu_to_le16(x) swap_16(x) -#define ohci_cpu_to_le32(x) swap_32(x) -#endif /* global ohci_t */ static ohci_t gohci; @@ -803,9 +798,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) } else td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); } -#ifdef CONFIG_MPC5200 td_list->hwNextTD = 0; -#endif } td_list->next_dl_td = td_rev; diff --git a/cpu/mpc5xxx/usb_ohci.h b/cpu/mpc5xxx/usb_ohci.h index 6eedbdd1d9..629b529a69 100644 --- a/cpu/mpc5xxx/usb_ohci.h +++ b/cpu/mpc5xxx/usb_ohci.h @@ -127,13 +127,8 @@ typedef struct td td_t; #define NUM_INTS 32 /* part of the OHCI standard */ struct ohci_hcca { __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) __u16 pad1; /* set to 0 on each frame_no change */ __u16 frame_no; /* current frame number */ -#else - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ -#endif __u32 done_head; /* info returned for an interrupt */ u8 reserved_for_hc[116]; } __attribute__((aligned(256))); |