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authorBin Meng <bmeng.cn@gmail.com>2019-07-18 10:34:30 +0300
committerTom Rini <trini@konsulko.com>2019-07-24 17:10:04 +0300
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tree93fd8dd3ae347d29432dedca846b701e21c13d14 /doc/README.ARC
parent862f9928aae1684b0aff55b42de09c1156d0f399 (diff)
downloadu-boot-3e12f7f03656ebab03c97913882abf83ca00c9f6.tar.xz
doc: arch: Convert README.ARC to reST
Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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-Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
-that SoC designers can optimize for a wide range of uses, from deeply embedded
-to high-performance host applications.
-
-More information on ARC cores avaialble here:
-http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
-
-Designers can differentiate their products by using patented configuration
-technology to tailor each ARC processor instance to meet specific performance,
-power and area requirements.
-
-The DesignWare ARC processors are also extendable, allowing designers to add
-their own custom instructions that dramatically increase performance.
-
-Synopsys' ARC processors have been used by over 170 customers worldwide who
-collectively ship more than 1 billion ARC-based chips annually.
-
-All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
-performance and code density for embedded and host SoC applications.
-
-The RISC microprocessors are synthesizable and can be implemented in any foundry
-or process, and are supported by a complete suite of development tools.
-
-The ARC GNU toolchain with support for all ARC Processors can be downloaded
-from here (available pre-built toolchains as well):
-
-https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases